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PDF HY27UG084G2M Data sheet ( Hoja de datos )
| Número de pieza | HY27UG084G2M | |
| Descripción | (HY27UGxx Series) 2G-Bit NAND Flash | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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om Preliminary
.c HY27UG(08/16)4G(2/D)M Series
t4U 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash
heeDocument Title
S4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Memory
.DataRevision History
wwRevision
w No.
History
Draft Date
Remark
0.0 Initial Draft.
m1) Add Errata
tWH
o0.1
Specification
15
.cRelaxed value
20
tWP
25
35
tWC
50
60
May. 13. 2005 Preliminary
May. 23. 2005 Preliminary
U1) Correct the Valid Blocks Number.
Valid Blocks (max)
t40.2 Before
4,098
eAfter
4,096
Jun. 13. 2005 Preliminary
e1) Add tRSBY (Table 11)
- tRSBY (Dummy Busy Time for Cache Read)
h0.3 - tRSBY is 5us (typ.)
JUn. 14. 2005 Preliminary
S2) Edit Figure 18, 19
3) Correct Extended Read Status Register Commands (Table. 19)
ta1) Add ULGA Package.
- Figures & texts are added.
a2) Correct the test Conditions (DC Characteristics table)
.DTest Conditions (ILI, ILO)
Before VIN=VOUT=0 to 3.6V
w0.4 After VIN=VOUT=0 to Vcc (max)
Sep. 02. 2005 Preliminary
3) Change AC Conditions table
w4) Add tWW parameter ( tWW = 100ns, min)
w- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
5) Edit System Interface Using CE don’t care Figures.
6) Correct Address Cycle Map.
Rev 0.5 / Oct. 2005
www.DataSheet4U.1com
1 page  
Preliminary
HY27UG(08/16)4G(2/D)M Series
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash
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Figure1: Logic Diagram
IO8 - IO15
IO7 - IO0
CLE
ALE
CE#
RE#
WE#
WP#
RB#
Vcc
Vss
NC
PRE
Data Input / Outputs (x16 only)
Data Input / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Power-On Read Enable, Lock Unlock
Table 1: Signal Names
Rev 0.5 / Oct. 2005
5
5 Page 
Preliminary
HY27UG(08/16)4G(2/D)M Series
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not
affect bus operations.
2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modifying operation (write/erase) the Write Protect pin
must be high. See figure 5 and table 12 for details of the timings requirements. Command codes are always applied on
IO7:0, disregarding the bus configuration (X8/x16).
2.2 Address Input.
Address Input bus operation allows the insertion of the memory address. To insert the 29 addresses needed to access
the 4Gbit 5 clock cycles are needed. Addresses are accepted with Chip Enable low, Address Latch Enable High, Com-
mand Latch Enable low and Read Enable high and latched on the rising edge of Write Enable. Moreover for commands
that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 6 and table 12 for details of
the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration (X8/16).
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command
Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure
7 and table 12 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to read data from the memory array and to check the status register content, the
lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write
Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 8,10,11 and table 12 for details
of the timings requirements.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the pro-
tection even during the power up.
2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
Rev 0.5 / Oct. 2005
11
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