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PDF IS42S16400 Data sheet ( Hoja de datos )
| Número de pieza | IS42S16400 | |
| Descripción | 1M-Bit x 16-Bit 4 4-Bank SDRAM | |
| Fabricantes | ISSI | |
| Logotipo |  |
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®
I1SSYM4Ne2CgSHBR1itO6shNe4xeO0t14U06USB.cDiotYsmNxA4MBICanRksAM(64-MBIT) ISSIFEATURES
S• Clock frequency: 166, 133, 100 MHz
ta• Fully synchronous; all signals referenced to a
.Dapositive clock edge
• Internal bank for hiding row access/precharge
ww• Single 3.3V power supply
w• LVTTL interface
m• Programmable burst length
o– (1, 2, 4, 8, full page)
.c• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
U• 4096 refresh cycles every 64 ms
t4• Random column address every clock cycle
e• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
eoperations capability
h• Burst termination by burst stop and precharge
command
S• Byte controlled by LDQM and UDQM
ta• Industrial temperature availability
a• Package: 400-mil 54-pin TSOP II
w.DPIN DESCRIPTIONS
wA0-A11
mBA0, BA1
w .coI/O0 to I/O15
UCLK
t4CKE
eeCS
hRAS
taSCAS
Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
FINAL PRODUCTION
MAY 2001
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42S16400 is organized
as 1,048,576 bits x 16-bit x 4-bank for improved
performance. ThesynchronousDRAMsachievehigh-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
VCC
I/O0
VCCQ
I/O1
I/O2
GNDQ
I/O3
I/O4
VCCQ
I/O5
I/O6
GNDQ
I/O7
VCC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 GND
53 I/O15
52 GNDQ
51 I/O14
50 I/O13
49 VCCQ
48 I/O12
47 I/O11
46 GNDQ
45 I/O10
44 I/O9
43 VCCQ
42 I/O8
41 GND
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 GND
WE
LDQM
UDQM
Vcc
GND
VccQ
GNDQ
NC
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
.DaThis document contains TARGET SPECIFICATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
wwwIntegrated Silicon Solution, Inc. — 1-800-379-4774
1
TARGET SPECIFICATION Rev. C
05/04/01
1 page  
IS42S16400
ISSI ®
enabled or disabled. AUTO PRECHARGE does not apply
except in full-page burst mode. Upon completion of the
READ or WRITE burst, a precharge of the bank/row that
is addressed is automatically performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generated during this operation. The stipulated period (tRC)
is required for a single refresh operation, and no other
commands can be executed during this period. This com-
mand is executed at least 4096 times every 64ms. During
an AUTO REFRESH command, address bits are “Don’t
Care”. This command corresponds to CBR Auto-refresh.
SELF REFRESH
During the SELF REFRESH operation, the row address to
be refreshed, the bank, and the refresh interval are
generated automatically internally. SELF REFRESH can
be used to retain data in the SDRAM without external
clocking, even if the rest of the system is powered down.
The SELF REFRESH operation is started by dropping the
CKE pin from HIGH to LOW. During the SELF REFRESH
operation all other inputs to the SDRAM become “Don’t
Care”.The device must remain in self refresh mode for a
minimum period equal to tRAS or may remain in self refresh
mode for an indefinite period beyond that.The SELF-
REFRESH operation continues as long as the CKE pin
remains LOW and there is no need for external control of
any other pins.The next command cannot be executed
until the device internal recovery period (tRC) has elapsed.
Once CKE goes HIGH, the NOP command must be
issued (minimum of two clocks) to provide time for the
completion of any internal refresh in progress. After the
self-refresh, since it is impossible to determine the ad-
dress of the last row to be refreshed, an AUTO-REFRESH
should immediately be performed for all addresses.
BURST TERMINATE
The BURST TERMINATE command forcibly terminates
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registered READ or WRITE command prior to the BURST
TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait
states.
LOAD MODE REGISTER
During the LOAD MODE REGSITER command the mode
register is loaded from A0-A11. This command can only
be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A11 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open for
accesses.
Integrated Silicon Solution, Inc. — 1-800-379-4774
TARGET SPECIFICATION Rev. C
05/04/01
5
5 Page 
IS42S16400
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCC MAX
VCCQ MAX
VIN
VOUT
PD MAX
ICS
TOPR
TSTG
Parameters
Maximum Supply Voltage
Maximum Supply Voltage for Output Buffer
Input Voltage
Output Voltage
Allowable Power Dissipation
Output Shorted Current
Operating Temperature
Com.
Ind.
Storage Temperature
Rating
–1.0 to +4.6
–1.0 to +4.6
–1.0 to +4.6
–1.0 to +4.6
1
50
0 to +70
–40 to +85
–55 to +150
Unit
V
V
V
V
W
mA
°C
°C
ISSI ®
DC RECOMMENDED OPERATING CONDITIONS(2) (At TA = 0 to +70°C)
Symbol
VCC, VCCQ
VIH
VIL
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
3.0
2.0
-0.3
Typ.
3.3
—
—
Max.
3.6
VCC + 0.3
+0.8
Unit
V
V
V
CAPACITANCE CHARACTERISTICS(1,2) (At TA = 0 to +25°C, Vcc = VccQ = 3.3 ± 0.3V, f = 1 MHz)
Symbol Parameter
Typ. Max. Unit
CIN1
CIN2
CI/O
Input Capacitance: A0-A11, BA0, BA1
Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM)
Data Input/Output Capacitance: I/O0-I/O15
—
—
—
4 pF
4 pF
5 pF
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. All voltages are referenced to GND.
Integrated Silicon Solution, Inc. — 1-800-379-4774
TARGET SPECIFICATION Rev. C
05/04/01
11
11 Page | ||
| Páginas | Total 54 Páginas | |
| PDF Descargar | [ Datasheet IS42S16400.PDF ] | |
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