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PDF COP411L Data sheet ( Hoja de datos )
| Número de pieza | COP411L | |
| Descripción | (COPxxxL) Single-Chip N-Channel Microcontrollers | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de COP411L (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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March 1992
COP410L COP411L COP310L COP311L
Single-Chip N-Channel Microcontrollers
General Description
The COP410L and COP411L Single-Chip N-Channel Micro-
controllers are members of the COPSTM family fabricated
using N-channel silicon gate MOS technology These Con-
troller Oriented Processors are complete microcomputers
containing all system timing internal logic ROM RAM and
I O necessary to implement dedicated control functions in a
variety of applications Features include single supply oper-
ation a variety of output configuration options with an in-
struction set internal architecture and I O scheme de-
signed to facilitate keyboard input display output and BCD
data manipulation The COP411L is identical to the
COP410L but with 16 I O lines instead of 19 They are an
appropriate choice for use in numerous human interface
control environments Standard test procedures and reliable
high-density fabrication techniques provide the medium to
large volume customers with a customized Controller Ori-
ented Processor at a low end-product cost
The COP310L and COP311L are exact functional equiva-
lents but extended temperature versions of COP410L and
COP411L respectively
The COP401L should be used for exact emulation
Features
Y Low cost
Y Powerful instruction set
Y 512 x 8 ROM 32 x 4 RAM
Y 19 I O lines (COP410L)
Y Two-level subroutine stack
Y 16 ms instruction time
Y Single supply operation (4 5V – 6 3V)
Y Low current drain (6 mA max)
Y Internal binary counter register with MICROWIRETM se-
rial I O capability
Y General purpose and TRI-STATE outputs
Y LSTTL CMOS compatible in and out
Y Direct drive of LED digit and segment lines
Y Software hardware compatible with other members of
COP400 family
Y Extended temperature range device
COP310L COP311L (b40 C to a85 C)
Block Diagram
FIGURE 1 COP410L
COPSTM and MICROWIRETM are trademarks of National Semiconductor Corporation
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL DD 6919
TL DD 6919 – 1
RRD-B30M105 Printed in U S A
1 page  
COP310L COP311L
DC Electrical Characteristics (Continued)
b40 C s TA s a85 C 4 5V s VCC s 5 5V unless othewise noted
Parameter
Conditions
Output Current Levels
Output Sink Current
SO and SK Outputs (IOL)
L0 – L7 Outputs G0 – G3 and
LSTTL D0 – D3 Outputs (IOL)
D0 – D3 Outputs with High
Current Options (IOL)
D0 – D3 Outputs with Very
High Current Options (IOL)
CKI (Single-Pin RC Oscillator)
CKO
Output Source Current
Standard Configuration
All Outputs (IOH)
Push-Pull Configuration
SO and SK Outputs (IOH)
LED Configuration L0 – L7
Outputs Low Current
Driver Option (IOH)
LED Configuration L0 – L7
Outputs High Current
Driver Option (IOH)
TRI-STATE Configuration
L0 – L7 Outputs Low
Current Driver Option (IOH)
TRI-STATE Configuration
L0 – L7 Outputs High
Current Driver Option (IOH)
Input Load Source Current
CKO Output
RAM Power Supply Option
Power Requirement
VCC e 5 5V VOL e 0 4V
VCC e 4 5V VOL e 0 4V
VCC e 5 5V VOL e 0 4V
VCC e 4 5V VOL e 0 4V
VCC e 5 5V VOL e 1 0V
VCC e 4 5V VOL e 1 0V
VCC e 5 5V VOL e 1 0V
VCC e 4 5V VOL e 1 0V
VCC e 4 5V VIH e 3 5V
VCC e 4 5V VOL e 0 4V
VCC e 5 5V VOH e 2 0V
VCC e 4 5V VOH e 2 0V
VCC e 5 5V VOH e 2 0V
VCC e 4 5V VOH e 1 0V
VCC e 5 5V VOH e 2 0V
VCC e 5 5V VOH e 2 0V
VCC e 5 5V VOH e 2 7V
VCC e 4 5V VOH e 1 5V
VCC e 5 5V VOH e 2 7V
VCC e 4 5V VOH e 1 5V
VCC e 5 0V VIL e 0V
VR e 3 3V
TRI-STATE Output Leakage
Current
Total Sink Current Allowed
All Outputs Combined
D Port
L7 – L4 G Port
L3 – L0
Any Other Pins
Total Source Current Allowed
All I O Combined
L7 – L4
L3 – L0
Each L Pin
Any Other Pins
5
Min
10
08
04
04
9
7
18
14
15
02
b55
b28
b1 1
b1 2
b0 7
b1 4
b0 6
b0 9
b1 2
b1 8
b10
b5
Max
b600
b350
b15
b30
b200
20
a5
100
100
4
4
15
120
60
60
25
15
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
5 Page 
L-Bus Considerations
False states may be generated on L0 – L7 during the execu-
tion of the CAMQ instruction The L-ports should not be
used as clocks for edge sensitive devices such as flip-flops
counters shift registers etc the following short program
that illustrates this situation
START
CLRA
ENABLE THE Q
LEI 4
REGISTER TO L LINES
LBI TEST
STII 3
AISC 12
LOOP
LBI TEST LOAD Q WITH X’C3
CAMQ
JP LOOP
Typical Performance Characteristics
In this program the internal Q register is enabled onto the L
lines and a steady bit pattern of logic highs is output on L0
L1 L6 L7 and logic lows on L2 – L5 via the two-byte CAMQ
instruction Timing constraints on the device are such that
the Q register may be temporarily loaded with the second
byte of the CAMQ opcode (X 3C) prior to receiving the valid
data pattern If this occurs the opcode will ripple onto the L
lines and cause negative-going glitches on L0 L1 L6 L7
and positive glitches on L2 – L5 Glitch durations are under
2 ms although the exact value may vary due to data pat-
terns processing parameters and L line loading These
false states are peculiar only to the CAMQ instruction and
the L lines
Input Current RESET SI
Input Current for L0 through
L7 when Output Programmed
Off by Software
Source Current for Standard
Output Configuration
Source Current for SO
and SK in Push-Pull
Configuration
Source Current for L0 through
L7 in TRI-STATE Configuration
(High Current Option)
Source Current for L0 through
L7 in TRI-STATE Configuration
(Low Current Option)
FIGURE 8a COP410L COP411L I O DC Current Characteristics
TL DD 6919 – 18
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet COP411L.PDF ] | |
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