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PDF CS5842 Data sheet ( Hoja de datos )
| Número de pieza | CS5842 | |
| Descripción | LCD Panel Timing Controller | |
| Fabricantes | Myson Century | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CS5842 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
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Centuerty4US.ceomm icondLCuDctPoarneInl Tci.ming ControllCerS(51854"2)GENERAL DESCRIPTION
heCS5842 is a TFT-LCD timing controller, which is
Sapplicable to 8-bit data XGA (1024*768), SXGA
ta(1280*1024).
aCS5842 can update the response timing for
display mode of XGA and SXGA automatically.
.DCS5842 provides a selectable polarity check
wfunction to inverse output data for EMI reducing,
wwhen the toggle number of ODD/EVEN RGB outputs
w is larger than 13.
FEATURES (continued)
• Correspondent to control timing & specific resolu-
tion for different Driver IC by changing a Mask:
1. can vary the pulse width & starting position
of LP signal and POL signal polarity
position changed along with LP signal
2. can vary the pulse width & starting position
of CLKV signal and tgs time
• Control ASIC output timing design is based on
Data Enable signals
FEATURES
m• Interface (5V/3.3V[CMOS] input, 3.3V[CMOS] out-
oput)
• Single (XGA2: 65MHz)/dual (XGA: 32.5MHz) 8-bit
.cData input; dual port 8-bit output; SXGA auto
detective
• Timing adjustable for horizontal clock output
• Embedded Power On Reset circuits, Vth=2.1V, tol-
erance ± 0.3V
• ESD spec. 4KV
• Power On Latch Up 200mA/6.6V
• Single 3.3V supply
• 144-pin LQFP package
t4UBLOCK DIAGRAM
heeDENA
VD
SHD
DCLK1
taINV
PNDCLK
PNVD
aPNHD
POLIN
ICMD(2~1)
.DDATAHT
SXMD
PNHMS
wPLMD
SCMD
wSET
TEST
CLKHT
wGT(2~1)
ODDRI(7~0)
mODDGI(7~0)
.coODDBI(7~0)
EVENRI(7~0)
UEVENGI(7~0)
t4EVENBI(7~0)
POWER ON RESET
STH1/STH8
POL/SHC
CLKV
GENERATOR GENERATOR GENERATOR
STV1/STV3
LP
CLKH
GENERATOR GENERATOR GENERATOR
CLKV
STV1
STV2
CLKH
STH1
STH8
LP
POL
SHC
RLSC
INPUT
SELECTOR
DATA-PATH
SAMPLE
POLARITY
DELAY
OUTPUT RGBD
SELECTOR
CS5842
ODDGO(7~0)
EVENGO(7~0)
ODDRO(7~0)
EVENRO(7~0)
ODDBO(7~0)
EVENBO(7~0)
HMS1
HMS2
SheeCentury Semiconductor, Inc.
taTaiwan:
aNo. 2, Industry East Rd. 3rd,
.DScience-Based Industrial Park, Hsin-Chu, Taiwan
wwwTel: 886-3-5784866 Fax: 886-3-5784349
USA:
1485 Saratoga Ave. #200
San Jose, CA, 95129
Tel: 408-973-8388 Fax: 408-973-9388
www.century-semi.com
Rev.0.2 October 2000
page 1 of 25
1 page  
Century Semiconductor Inc.
CS5842
Name
STH1
CLKV
STV3
STV1
RLSC
SET
GT(2-1)
SXMD
PNVD
PNHD
GND
DCLK1
DATAHT
DENA
VD
HD
INV
I/O Pin
Block
Type
Description
Note
O 90 P3OUTRB START PULSE (S1→ S8) of Source Driver IC.
O 91 P3OUTRB SHIFT CLOCK output for Gate Driver IC.
O 92 P3OUTRB START PULSE (G3→ G1) of Gate Driver IC.
O 93 P3OUTRB START PULSE (G1→ G3) of Gate Driver IC.
O 94 P3OUTRB R/L Output for Source Driver IC.
I 95 P5INPHU ASIC internal reset setting.
LOW = initialization, is usually OPEN.
20kΩ pull up
(OPEN)
I 96-97 P5INPHU Adjust CLKV Clock Timing (GT1: LSB; GT2: MSB).
1. ICMD2 = OPEN, ICMD1 = LOW: IC1
CLKV rising edge generated before LP falling edge.
4 steps: 0.5 µs (i.e. 17CLKH) each step, 2.5~4.0µs
2. ICMD2 = OPEN, ICMD1 = OPEN: IC2
CLKV rising edge generated before LP rising edge.
4 steps: 0.5 µs (i.e. 17CLKH) each step, 2.5~4.0µs
20kΩ pull up
(GT1:OPEN
GT2:0Ω
default:
01 ⇒ 3µs)
3. ICMD2 = LOW, ICMD1 = LOW: IC3
CLKV rising edge generated before LP falling edge.
4 steps: 0.5 µs (i.e. 17CLKH) each step, 2.5~4.0µs
4. ICMD2 = LOW, ICMD1 = OPEN: IC4
CLKV rising edge generated before LP falling edge.
4 steps: 0.5 µs (i.e. 17CLKH) each step, 2.5~4.0µs
I 98 P5INPHU XGA/XGA2 switch selection
SXMD = OPEN; XGA(32.5MHz)
SXMD = LOW; XGA2(65MHz)
20kΩ pull up
(OPEN)
I 99 P5INPHU Vertical sync signal polarity setting.
Low = inverted; Open = non-inverted.
20kΩ pull up
(OPEN)
I 100 P5INPHU Horizontal sync signal polarity setting.
Low = inverted; Open = non-inverted.
20kΩ pull up
(OPEN)
101 Ground
I 102 P5INPMN Dot Clock input.
XGA: 32.5MHz
5V tolerant
I 103 P5INPHU Adjust Data output Timing
1. DATAHT = OPEN 0.0ns/2.2ns/3.2ns delay
2. DATAHT = LOW 0.0ns/2.2ns/4.4ns delay
20kΩ pull up
(OPEN)
I 104 P5INPMN Data Enable signal input.
DCLK1 synchronized. 5V tolerant
I 105 P5INPMN Vertical sync signal input.
DCLK1 synchronized. 5V tolerant
I 106 P5INPMN Horizontal sync signal input.
DCLK1 synchronized. 5V tolerant
I 107 P5INPMN Data input of polarity control.
High = polarity of input data been inverted.
Low = polarity of input data not been inverted.
5V tolerant
page 5 of 25
5 Page 
Century Semiconductor Inc.
CS5842
Input Timing Specification
Symbol
Item
f(DCLK1) Input Clock frequency
tw(DCLK1) Input Clock period
twH(DCLK1) Input Clock High time
twL(DCLK1) Input Clock Low time
tst(DI) Input Data Setup time
thd(DI) Input Data Hold time
tst(DENA) Input Data Enable signal Setup time
thd(DENA) Input Data Enable signal Hold time
tst(HD) Horizontal Sync signal Setup time
thd(HD) Horizontal Sync signal Hold time
tst(VD) Vertical Sync signal Setup time
thd(VD) Vertical Sync signal Hold time
tw(DENA) Input Data Enable signal High time
tbh(DENAH)
Input Data Enable Horizontal Sync signal
Blanking time
f(HD) Horizontal Sync signal
tw(HD) HD horizontal sync signal Low time
tf(HD) Horizontal front porch
tb(HD) Horizontal back porch
tbh(DENAV)
Input Data Enable Horizontal Sync signal
Blanking time
f(VD) Vertical sync signal
tw(VD) VD Vertical Sync signal Low time
tf(VD) Vertical front porch
tb(VD) Vertical back porch
Note: HIGH, LOW level of input signal: VIL = 0.8V, VIH = 2.2V.
Specification
Min Typ Max
30 32.5 54/80
12.5 30.8 33.3
0.3 -
-
0.3 -
-
2.3 -
-
7.3 -
-
2.3 -
-
7.3 -
-
2.3 -
-
7.3 -
-
2.3 -
-
7.3 -
-
512 512 640
6- -
-
48.25
62.5
1- -
0- -
6- -
4- -
55 60 75
1- -
0- -
4- -
Unit
MHz
ns
CLK
CLK
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
KHz
CLK
CLK
CLK
H
Hz
H
H
H
page 11 of 25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet CS5842.PDF ] | |
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