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PDF MC14513B Data sheet ( Hoja de datos )
| Número de pieza | MC14513B | |
| Descripción | BCD-To-Seven Segment Latch/Decoder/Driver | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC14513B
BCD-To-Seven Segment
Latch/Decoder/Driver
CMOS MSI
(Low–Power Complementary MOS)
The MC14513B BCD–to–seven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic structure.
The circuit provides the functions of a 4–bit storage latch, an 8421
BCD–to–seven segment decoder, and has output drive capability. Lamp
test (LT), blanking (BI), and latch enable (LE) inputs are used to test the
display, to turn–off or pulse modulate the brightness of the display, and
to store a BCD code, respectively. The Ripple Blanking Input (RBI) and
Ripple Blanking Output (RBO) can be used to suppress either leading
or trailing zeroes. It can be used with seven–segment light emitting
diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal
readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.
• Low Logic Circuit Power Dissipation
• High–current Sourcing Outputs (Up to 25 mA)
• Latch Storage of Binary Input
• Blanking Input
• Lamp Test Provision
• Readout Blanking on all Illegal Input Combinations
• Lamp Intensity Modulation Capability
• Time Share (Multiplexing) Capability
• Adds Ripple Blanking In, Ripple Blanking Out to MC14511B
• Supply Voltage Range = 3.0 V to 18 V
• Capable of Driving Two Low–Power TTL Loads, One Low–power
Schottky TTL Load to Two HTL Loads Over the Rated Temperature
Range.
MAXIMUM RATINGS (Voltages Referenced to VSS) (1.)
Symbol
Parameter
Value
Unit
VDD DC Supply Voltage Range
– 0.5 to +18.0
V
Vin
Input Voltage Range, All Inputs – 0.5 to VDD + 0.5
V
I DC Current Drain per Input Pin 10 mA
PD Power Dissipation,
per Package (2.)
500 mW
TA
Tstg
IOHmax
Operating Temperature Range
Storage Temperature Range
Maximum Continuous Output
Drive Current (Source) per Output
– 55 to +125
– 65 to +150
25
°C
°C
mA
POHmax Maximum Continuous Output
Power (Source) per Output (3.)
50
mW
http://onsemi.com
PDIP–18
P SUFFIX
CASE 707
MARKING
DIAGRAMS
18
MC14513BCP
AWLYYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14513BCP
PDIP–18
20/Rail
This device contains protection circuitry to protect
the inputs against damage due to high static voltages
or electric fields. However, it is advised that normal
precautions be taken to avoid application of any volt-
age higher than maximum rated voltages to this high–
impedance circuit. A destructive high current mode
v vmay occur if Vin and Vout are not constrained to the
range VSS (Vin or Vout) VDD.
Due to the sourcing capability of this circuit, dam-
age can occur to the device if VDD is applied, and the
outputs are shorted to VSS and are at a logical 1 (See
Maximum Ratings).
Unused inputs must always be tied to an appropri-
ate logic voltage level (e.g., either VSS or VDD).
1. Maximum Ratings are those values beyond which
damage to the device may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C
From 65_C To 125_C
3. POHmax = IOH (VDD – VOH)
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14513B/D
1 page  
MC14513B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSWITCHING CHARACTERISTICS (7.) (CL =50pF,TA=25_C)
VDD
All Types
Characteristic
Symbol
Vdc
Min
Typ
Max Unit
Output Rise Time — Segment Outputs
tTLH
ns
5.0 — 40 80
10 — 30 60
15 — 25 50
Output Rise Time — RBO Output
tTLH
ns
5.0 — 480 960
10 — 240 480
15 — 190 380
Output Fall Time — Segment Outputs (7.)
tTHL = (1.5 ns/pF) CL + 50 ns
tTHL = (0.75 ns/pF) CL + 37.5 ns
tTHL = (0.55 ns/pF) CL + 37.5 ns
Output Fall Time — RBO Outputs
tTHL = (3.25 ns/pF) CL + 107.5 ns
tTHL = (1.35 ns/pF) CL + 67.5 ns
tTHL = (0.95 ns/pF) CL + 62.5 ns
Propagation Delay Time — A, B, C, D Inputs (7.)
tPLH = (0.40 ns/pF) CL + 620 ns
tPLH = (0.25 ns/pF) CL + 237.5 ns
tPLH = (0.20 ns/pF) CL + 165 ns
tTHL
ns
5.0 — 125 250
10 — 75 150
15 — 65 130
tTHL
ns
5.0 — 270 540
10 — 135 270
15 — 110 220
tPLH
ns
5.0 — 640 1280
10 — 250 500
15 — 175 350
tPHL = (1.3 ns/pF) CL + 655 ns
tPHL = (0.60 ns/pF) CL + 260 ns
tPHL = (0.35 ns/pF) CL + 182.5 ns
tPHL
5.0
—
720
1440
ns
10 — 290 580
15 — 200 400
Propagation Delay Time — RBI and BI Inputs (7.)
tPLH = (1.05 ns/pF) CL + 547.5 ns
tPLH = (0.45 ns/pF) CL + 177.5 ns
tPLH = (0.30 ns/pF) CL + 135 ns
tPHL = (0.85 ns/pF) CL + 442.5 ns
tPHL = (0.45 ns/pF) CL + 177.5 ns
tPHL = (0.35 ns/pF) CL + 142.5 ns
Propagation Delay Time — LT Input (7.)
tPLH = (0.45 ns/pF) CL + 290.5 ns
tPLH = (0.25 ns/pF) CL + 112.5 ns
tPLH = (0.20 ns/pF) CL + 80 ns
tPHL = (1.3 ns/pF) CL + 248 ns
tPHL = (0.45 ns/pF) CL + 102.5 ns
tPHL = (0.35 ns/pF) CL + 72.5 ns
tPLH
ns
5.0 — 600 750
10 — 200 300
15 — 150 220
tPHL 5.0 — 485 970 ns
10 — 200 400
15 — 160 320
tPLH
ns
5.0 — 313 625
10 — 125 250
15 — 90 180
tPHL 5.0 — 313 625 ns
10 — 125 250
15 — 90 180
Setup Time
tsu
5.0 100 —
— ns
10 40 — —
15 30 — —
Hold Time
th 5.0 60 — — ns
10 40 — —
15 30 — —
Latch Enable Pulse Width
tWL(LE) 5.0 520 260 — ns
10 220 110 —
15 130 65
—
7. The formulas given are for the typical characteristics only.
http://onsemi.com
5
5 Page 
Notes
MC14513B
http://onsemi.com
11
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| PDF Descargar | [ Datasheet MC14513B.PDF ] | |
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