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PDF MC33298 Data sheet ( Hoja de datos )
| Número de pieza | MC33298 | |
| Descripción | OCTAL SERIAL SWITCH (SPI Input/Output) | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Order this document by MC33298/D
MC33298
Octal Serial Switch with
Serial Peripheral Interface I/O
The MC33298 is an eight output low side power switch with 8 bit serial input
control. The MC33298 is a versatile circuit designed for automotive
applications, but is well suited for other environments. The MC33298
incorporates SMARTMOS™ technology, with CMOS logic, bipolar/MOS
analog circuitry, and DMOS power MOSFETs. The MC33298 interfaces
directly with a microcontroller to control various inductive or incandescent
loads. The circuit’s innovative monitoring and protection features are: very low
standby current, cascadable fault reporting, internal 65 V clamp on each
output, output specific diagnostics, and independent shutdown of outputs. The
MC33298 is parametrically specified over a temperature range of – 40°C ≤ TA
≤ +125°C ambient temperature and 9.0 V ≤ VPWR ≤ 16 V supply. The
economical 20 pin DIP and SO–24 wide body surface mount plastic packages
make the MC33298 very cost effective.
• Designed to Operate Over Wide Supply Voltages of 5.5 V to 26.5 V
• Interfaces Directly to Microprocessor Using SPI Protocol
• SPI Communication for Control and Fault Reporting
• 8–Bit Serial I/O is CMOS Compatible
• 3.0 A Peak Current Outputs with Maximum RDS(on) of 0.45 Ω at 25°C
• Outputs are Current Limited to 3.0 A to 6.0 A for Driving Incandescent
Lamp Loads
• Output Voltages Clamped to 65 V During Inductive Switching
• Maximum Sleep Current (IPWR) of 50 µA with VDD ≤ 2.0 V
• Maximum of 4.0 mA IDD During Operation
• Maximum of 2.0 mA IPWR During Operation with All Outputs “On”
• Open Load Detection (Outputs “Off”)
• Overvoltage Detection and Shutdown
• Each Output has Independent Over Temperature Detection and Shutdown
• Output Mode Programmable for Sustained Current Limit or Shutdown
• Short Circuit Detect and Shutdown with Automatic Retry for Every
Write Cycle
• Serial Operation Guaranteed to 2.0 MHz
SFPD
Micro–
controller
with Bus
SFPD
CSB
SCLK
SI
Reset
SO
Simplified Application
VDD VPWR
CMOS
Input
Logic
CMOS
Serial Shift
Registers
and
Latches
Updrain
DMOS
Output
Switches
and
Sense
Circuits
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
+Vbat
OCTAL SERIAL SWITCH
(SPI Input/Output)
SEMICONDUCTOR
TECHNICAL DATA
20
1
P SUFFIX
PLASTIC PACKAGE
CASE 738
DIP (16+2+2)
24
1
DW SUFFIX
PLASTIC PACKAGE
CASE 751E
SOP (16+4+4)L
PIN CONNECTIONS
DIP Function SOP–24L
1 Output 7 1
2 Output 6 2
3 SCLK 3
4 SI 4
5 Ground 5
6 Ground 6
– Ground 7
– Ground 8
7 SO 9
8
CSB
10
9
Output 5
11
10 Output 4 12
11 Output 3 13
12 Output 2 14
13 SFPD 15
14 VDD 16
15 Ground 17
16 Ground 18
–
Ground
19
–
Ground
20
17 VPWR 21
18 Reset 22
19 Output 1 23
20 Output 0 24
ORDERING INFORMATION
Device
Tested Operating
Temperature Range Package
This device contains 1,200 active transistors.
Gnd
MC33298P
DIP
MC33298DW TC = – 40° to +125°C SOP–24L
MOTOROLA ANALOG IC DEVICE DATA
© Motorola, Inc. 1996
Rev 2
1
1 page  
MC33298
STATIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions of 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V,
– 40°C ≤ TC ≤ 125°C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ Max Unit
DIGITAL INTERFACE
Input Logic High Voltage (Note 1)
Input Logic Low Voltage (Note 2)
Input Logic Voltage Hysteresis (Note 3)
Input Logic Current (Note 4)
Reset Pull–Up Current (Reset = 0.7 VDD)
SFPD Pull–Down Current (SFPD = 0.2 VDD)
SO High State Output Voltage (IOH = 1.0 mA)
SO Low State Output Voltage (IOL = –1.6 mA)
SO Tri–State Leakage Current (CSB = 0.7 VDD, 0 V ≤ VSO ≤ VDD)
Input Capacitance (0 V ≤ VDD ≤ 5.5 V) (Note 5)
VIH
VIL
VI(hys)
IIN
IRSTB
ISFPD
VSOH
VSOL
ISOT
CIN
0.7 –
0.0 –
50 100
–10 0
10 22
10 22
VDD –1.0 V VDD – 0.6 V
– 0.2
– 10 0
––
1.0
0.2
500
10
50
50
–
0.4
10
12
VDD
VDD
mV
µA
µA
µA
V
V
µA
pF
SO Tri–State Capacitance (0 V ≤ VDD ≤ 5.5 V) (Note 6)
CSOT
–
– 20 pF
NOTES: 1. Upper logic threshold voltage range applies to SI, CSB, SCLK, Reset, and SFPD input signals.
2. Lower logic threshold voltage range applies to SI, CSB, SCLK, Reset, and SFPD input signals.
3. Only the SFPD and Reset inputs have hysteresis. This parameter is guaranteed by design but is not production tested.
4. Input current of SCLK, SI, and CSB logic control inputs.
5. Input capacitance of SI, CSB, SCLK, Reset, and SFPD for 0 V ≤ VDD ≤ 5.5 V. This parameter is guaranteed by design, but is not production tested.
6. Tri–state capacitance of SO for 0 V ≤ VDD ≤ 5.5 V. This parameter is guaranteed by design but is not production tested.
Figure 2. Input Timing Switch Characteristics
RSTB
0.2 VDD
CSB
SCLK
SI
twRSTB
0.2 VDD
tlead
0.7 VDD
twSCLKH
Don’t Care
0.2 VDD
tSISU
0.7 VDD
Valid
0.2 VDD
tr
twSCLKL
tSI(hold)
Don’t Care
tlag
tf
Valid
VIH
VIL
VIH
VIL
VIH
VIL
Don’t Care
VIH
VIL
MOTOROLA ANALOG IC DEVICE DATA
5
5 Page 
MC33298
PIN FUNCTION DESCRIPTION
CSB Pin
The system MCU selects the MC33298 to be
communicated with through the use of the CSB pin.
Whenever the pin is in a logic low state, data can be
transferred from the MCU to the MC33298 and vise versa.
Clocked–in data from the MCU is transferred from the
MC33298 shift register and latched into the power outputs on
the rising edge of the CSB signal. On the falling edge of the
CSB signal, drain status information is transferred from the
power outputs and loaded into the device’s shift register. The
CSB pin also controls the output driver of the serial output
pin. Whenever the CSB pin goes to a logic low state, the SO
pin output driver is enabled allowing information to be
transferred from the MC33298 to the MCU. To avoid any
spurious data, it is essential that the high–to–low transition of
the CSB signal occur only when SCLK is in a logic low state.
SCLK Pin
The system clock pin (SCLK) clocks the internal shift
registers of the MC33298. The serial input pin (SI) accepts
data into the input shift register on the falling edge of the
SCLK signal while the serial output pin (SO) shifts data
information out of the shift register on the rising edge of the
SCLK signal. False clocking of the shift register must be
avoided to guarantee validity of data. It is essential that the
SCLK pin be in a logic low state whenever chip select bar pin
(CSB) makes any transition. For this reason, it is
recommended though not necessary, that the SCLK pin be
kept in a low logic state as long as the device is not accessed
(CSB in logic high state). When CSB is in a logic high state,
any signal at the SCLK and SI pin is ignored and SO is
tristated (high impedance). See the Data Transfer Timing
diagram of Figure 16.
SI Pin
This pin is for the input of serial instruction data. SI
information is read in on the falling edge of SCLK. A logic high
state present on this pin when the SCLK signal rises will
program a specific output “off,” and in turn, turns “off” the
specific output on the rising edge of the CSB signal.
Conversely, a logic low state present on the SI pin will
program the output “on,” and in turn, turns “on” the specific
output on the rising edge of the CSB signal. To program the
eight outputs of the MC33298 “on” or “off,” an eight bit serial
stream of data is required to be entered into the SI pin
starting with Output 7, followed by Output 6, Output 5, etc., to
Output 0. For each rise of the SCLK signal, with CSB held in
a logic low state, a databit instruction (“on” or “off”) is loaded
into the shift register per the databit SI state. The shift register
is full after eight bits of information have been entered. To
preserve data integrity, care should be taken to not transition
SI as SCLK transitions from a low to high logic state.
SO Pin
The serial output (SO) pin is the tri–stateable output from
the shift register. The SO pin remains in a high impedance
state until the CSB pin goes to a logic low state. The SO data
reports the drain status, either high or low. The SO pin
changes state on the rising edge of SCLK and reads out on
the falling edge of SCLK. When an output is “off” and not
faulted, the corresponding SO databit is a high state. When
an output is “on,” and there is no fault, the corresponding
databit on the SO pin will be a low logic state. The SI/SO
shifting of data follows a first–in–first–out protocol with both
input and output words transferring the Most Significant Bit
(MSB) first. The SO pin is not affected by the status of the
Reset pin.
Reset Pin
The MC33298 Reset pin is active low and used to clear the
SPI shift register and in doing so sets all output switches “off.”
With the device in a system with an MCU; upon initial system
power up, the MCU holds the Reset pin of the device in a
logic low state ensuring all outputs to be “off” until both the
VDD and VPWR pin voltages are adequate for predictable
operation. After the MC33298 is reset, the MCU is ready to
assert system control with all output switches initially “off.” If
the VPWR pin of the MC33298 experiences a low voltage,
following normal operation, the MCU should pull the Reset
pin low so as to shutdown the outputs and clear the input data
register. The Reset pin is active low and has an internal
pull–up incorporated to ensure operational predictability
should the external pull–up of the MCU open circuit. The
internal pull–up is only 20 µA to afford safe and easy
interfacing to the MCU. The Reset pin of the MC33298
should be pulled to a logic low state for a duration of at least
250 ns to ensure reliable reset.
A simple power “on” reset delay of the system can be
programmed through the use of an RC network comprised of
a shunt capacitor from the Reset pin to Ground and a resistor
to VDD (See Figure 15). Care should be exercised to ensure
proper discharge of the capacitor so as to not adversely
delay the reset nor damage the MCU should the MCU pull the
Reset line low and yet accomplish initialization for turn “on”
delay. It may be easier to incorporate delay into the software
program and use a parallel port pin of the MCU to control the
MC33298 Reset pin.
Figure 15. Power “On” Reset
VDD
Reset
MCU
RDLY
CDLY
20 µA
Reset
MC33298
SFPD Pin
The Short Fault Protect Disable (SFPD) pin is used to
disable the over current latch–off. This feature allows control
of incandescent loads where in–rush currents exceed the
device’s analog current limits. Essentially the SFPD pin
determines whether the MC33298 output(s) will instantly shut
down upon sensing an output short or remain “on” in a
current limiting mode of operation until the output short is
removed or thermal shutdown is reached. If the SFPD pin is
tied to VDD = 5.0 V the MC33298 output(s) will remain “on” in
a current limited mode of operation upon encountering a load
short to supply. If the SFPD pin is grounded, a short circuit
will immediately shut down only the output affected. Other
outputs not having a fault condition will operate normally. The
short circuit operation is addressed in more detail later.
MOTOROLA ANALOG IC DEVICE DATA
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MC33298.PDF ] | |
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