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PDF LT1812CS8 Data sheet ( Hoja de datos )
| Número de pieza | LT1812CS8 | |
| Descripción | 3mA/ 100MHz/ 750V/us Operational Amplifier with Shutdown | |
| Fabricantes | Linear Technology | |
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FEATURES
s 100MHz Gain Bandwidth
s 750V/µs Slew Rate
s 3.6mA Maximum Supply Current
s 50µA Supply Current in Shutdown
s 8nV/√Hz Input Noise Voltage
s Unity-Gain Stable
s 1.5mV Maximum Input Offset Voltage
s 4µA Maximum Input Bias Current
s 400nA Maximum Input Offset Current
s 40mA Minimum Output Current, VOUT = ±3V
s ±3.5V Minimum Input CMR, VS = ±5V
s 30ns Settling Time to 0.1%, 5V Step
s Specified at ±5V, Single 5V Supplies
s Operating Temperature Range: – 40°C to 85°C
U
APPLICATIO S
s Wideband Amplifiers
s Buffers
s Active Filters
s Video and RF Amplification
s Cable Drivers
s Data Acquisition Systems
LT1812
3mA, 100MHz, 750V/µs
Operational Amplifier
with Shutdown
DESCRIPTIO
The LT®1812 is a low power, high speed, very high slew
rate operational amplifier with excellent DC performance.
The LT1812 features reduced supply current, lower input
offset voltage, lower input bias current and higher DC gain
than other devices with comparable bandwidth. A power
saving shutdown feature reduces supply current to 50µA.
The circuit topology is a voltage feedback amplifier with
the slewing characteristics of a current feedback amplifier.
The output drives a 100Ω load to ±3.5V with ±5V supplies.
On a single 5V supply, the output swings from 1.1V to 3.9V
with a 100Ω load connected to 2.5V. The amplifier is stable
with a 1000pF capacitive load which makes it useful in
buffer and cable driver applications.
The LT1812 is manufactured on Linear Technology’s
advanced low voltage complementary bipolar process.
The dual version is the LT1813. For higher supply voltage
single, dual and quad operational amplifiers with up to
70MHz gain bandwidth, see the LT1351 through LT1365
data sheets.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
4MHz, 4th Order Butterworth Filter
232Ω
232Ω
VIN
665Ω
220pF
– 47pF
LT1812
+
274Ω
274Ω 562Ω
470pF
– 22pF
LT1812
+
VOUT
1812 TA01
Filter Frequency Response
10
0
–10
–20
–30
–40
–50
–60
–70 VS = ±5V
–80 VIN = 600mVP-P
PEAKING < 0.12dB
–90
0.1 1
10
FREQUENCY (MHz)
100
1812 TA02
1
1 page  
LT1812
ELECTRICAL CHARACTERISTICS –40°C ≤ TA ≤ 85°C. VS = ±5V, VCM = 0V unless otherwise noted (Note 8).
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Minimum Supply Voltage
±2 V
PSRR
AVOL
VOUT
IOUT
ISC
SR
GBW
ISHDN
IS
Power Supply Rejection Ratio
Large-Signal Voltage Gain
Maximum Output Swing
Maximum Output Current
Output Short-Circuit Current
Slew Rate
Gain Bandwidth Product
SHDN Pin Current
Supply Current
VS = ±2V to ±5.5V
VOUT = ±3V, RL = 500Ω
VOUT = ±3V, RL = 100Ω
RL = 500Ω, 30mV Overdrive
RL = 100Ω, 30mV Overdrive
VOUT = ±3V, 30mV Overdrive
VOUT = 0V, 1V Overdrive (Note 3)
AV = – 1 (Note 5)
f = 200kHz
SHDN > V – + 2.0V (On)
SHDN < V – + 0.4V (Off)
SHDN > V – + 2.0V (On)
SHDN < V – + 0.4V (Off)
75
0.8
0.6
± 3.60
± 3.15
± 30
± 55
350
60
– 200
dB
V/mV
V/mV
V
V
mA
mA
V/µs
MHz
±2 µA
µA
5 mA
200 µA
– 40°C ≤ TA ≤ 85°C, VS = 5V, VCM = 2.5V, RL to 2.5V unless otherwise noted (Note 8).
SYMBOL PARAMETER
CONDITIONS
VOS
∆VOS/∆T
IOS
IB
VCM
Input Offset Voltage
Input Offset Voltage Drift
Input Offset Current
Input Bias Current
Input Voltage Range (Positive)
Input Voltage Range (Negative)
(Note 4)
(Note 7)
CMRR
AVOL
VOUT
IOUT
ISC
SR
GBW
ISHDN
IS
Common Mode Rejection Ratio
Large-Signal Voltage Gain
Maximum Output Swing (Positive)
Maximum Output Swing (Negative)
Maximum Output Current
Output Short-Circuit Current
Slew Rate
Gain Bandwidth Product
SHDN Pin Current
Supply Current
VCM = 1.5V to 3.5V
VOUT = 1.5V to 3.5V, RL = 500Ω
VOUT = 2.0V to 3.0V, RL = 100Ω
RL = 500Ω, 30mV Overdrive
RL = 100Ω, 30mV Overdrive
RL = 500Ω, 30mV Overdrive
RL = 100Ω, 30mV Overdrive
VOUT = 3.5V or 1.5V, 30mV Overdrive
VOUT = 2.5V, 1V Overdrive (Note 3)
AV = – 1 (Note 5)
f = 200kHz
SHDN > V – + 2.0V (On)
SHDN < V – + 0.4V (Off)
SHDN > V – + 2.0V (On)
SHDN < V – + 0.4V (Off)
MIN TYP MAX
3.5
10 30
600
±6
3.5
1.5
70
0.6
0.4
3.7
3.5
1.3
1.5
± 17
± 40
125
50
– 100
±2
5
100
UNITS
mV
µV/°C
nA
µA
V
V
dB
V/mV
V/mV
V
V
V
V
mA
mA
V/µs
MHz
µA
µA
mA
µA
Note 1: Absolute Maximum Ratings are those values beyond which the life of
the device may be impaired.
Note 2: Differential inputs of ±3V are appropriate for transient operation only,
such as during slewing. Large sustained differential inputs can cause
excessive power dissipation and may damage the part.
Note 3: A heat sink may be required to keep the junction temperature below
absolute maximum when the output is shorted indefinitely.
Note 4: Input offset voltage is pulse tested and is exclusive of warm-up drift.
Note 5: Slew rate is measured between ±2V on the output with ±3V input for
±5V supplies and 2VP-P on the output with a 3VP-P input for single 5V
supplies.
Note 6: Full power bandwidth is calculated from the slew rate:
FPBW = SR/2πVP.
Note 7: This parameter is not 100% tested.
Note 8: The LT1812C is guaranteed to meet specified performance from
0°C to 70°C. The LT1812C is designed, characterized and expected to meet
specified performance from –40°C to 85°C but is not tested or QA sampled
at these temperatures. The LT1812I is guaranteed to meet specified
performance from –40°C to 85°C.
Note 9: θJA is specified for a 2500mm2 board covered with 2 oz copper on
both sides. Thermal resistance varies, depending upon the amount of PC
board metal attached to the device. For this package in particular, power is
dissipated primarily through Pin 4, which should therefore, have a good
thermal connection to a copper plane.
5
5 Page 
LT1812
APPLICATIO S I FOR ATIO
junction temperature (TJ) is calculated from the ambient
temperature (TA) and power dissipation (PD) as follows:
LT1812CS8: TJ = TA + (PD • 80°C/W) (Note 9)
Power dissipation is composed of two parts. The first is
due to the quiescent supply current and the second is due
to on-chip dissipation caused by the load current. The
worst-case load induced power occurs when the output
voltage is at 1/2 of either supply voltage (or the maximum
swing if less than 1/2 supply voltage). Therefore PDMAX is:
PDMAX = (V + – V –)(ISMAX) + (V +/2)2/RL or
PDMAX = (V + – V –)(ISMAX) + (V + – VOMAX)(VOMAX/RL)
Example: LT1812CS8 at 70°C, VS = ±5V, RL = 100Ω
PDMAX = (10V)(4.5mA) + (2.5V)2/100Ω = 108mW
TJMAX = 70°C + (108mW)(80°C/W) = 79°C
Circuit Operation
The LT1812 circuit topology is a true voltage feedback
amplifier that has the slewing behavior of a current feed-
back amplifier. The operation of the circuit can be under-
stood by referring to the Simplified Schematic. The inputs
are buffered by complementary NPN and PNP emitter
followers that drive a 300Ω resistor. The input voltage
appears across the resistor generating currents that are
mirrored into the high impedance node. Complementary
followers form an output stage that buffers the gain node
from the load. The bandwidth is set by the input resistor
and the capacitance on the high impedance node. The slew
rate is determined by the current available to charge the
gain node capacitance. This current is the differential input
voltage divided by R1, so the slew rate is proportional to
the input. Highest slew rates are therefore seen in the
lowest gain configurations. The RC network across the
output stage is bootstrapped when the amplifier is driving
a light or moderate load and has no effect under normal
operation. When driving capacitive loads (or a low value
resistive load) the network is incompletely bootstrapped
and adds to the compensation at the high impedance
node. The added capacitance slows down the amplifier
which improves the phase margin by moving the unity-
gain cross away from the pole formed by the output
impedance and the capacitive load. The zero created by the
RC combination adds phase to ensure that the total phase
lag does not exceed 180 degrees (zero phase margin) and
the amplifier remains stable. In this way, the LT1812 is
stable with up to 1000pF capacitive loads in unity gain, and
even higher capacitive loads in higher closed-loop gain
configurations.
WW
SI PLIFIED SCHEMATIC
V+
RB
SHDN
V–
–IN
BIAS
CONTROL
R1
300Ω
+IN
C
RC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
CC
OUT
1812 SS
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LT1812CS8.PDF ] | |
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