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PDF STLC2500 Data sheet ( Hoja de datos )
| Número de pieza | STLC2500 | |
| Descripción | BLUETOOTH SINGLE CHIP | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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STLC2500
1 FEATURES
■ Bluetooth™ specification compliance: V1.1 and
V1.2
■ Ericsson Licensing Technology Baseband Core
(EBC)
■ Point-to-point, point-to-multi-point (up to 7
slaves) and scatternet capability
■ Asynchronous Connection Oriented (ACL)
logical transport link
■ Synchronous Connection Oriented (SCO) link:
2 simultaneous SCO channels
■ Support Pitch-Period Error Concealment (PPEC)
– Improves speech quality in the vicinity of in-
terference
– Improves coexistence with WLAN
– Works at receiver, no Bluetooth implication
■ Adaptive Frequency Hopping (AFH): hopping
kernel, channel assessment as Master and as
Slave
■ Faster Connection: Interlaced scan for Page
and Inquiry scan, first FHS without random back
off, RSSI used to limit range
■ Extended SCO (eSCO) links
■ HW support for packet types
– ACL: DM1, 3, 5 and DH1, 3, 5
– SCO: HV1, 3 and DV
– eSCO: EV3, 5
■ Clock support
– System clock input (digital or sine wave) at
13, 26, 19.2 or 38.4 MHz
– LPO clock input at 3.2, 16.384, 32 or 32.768 kHz
■ ARM7TDMI CPU
– 32-bit Core
– AMBA (AHB-APB) bus configuration
■ Patch RAM capability
■ Memory organization
– On chip RAM, including provision for patches
– On chip ROM, preloaded with SW up to HCI
■ Communication interfaces
– Fast UART
– PCM interface
– 4 programmable GPIOs
– External interrupts possible through the GPIOs
– Fast master I2C interface
■ Efficient support for WLAN coexistence in
collocated scenario
■ Ciphering support up to 128 bits key
■ Software support
– Lower level stack (up to HCI)
– HCI Transport Layer: H4 (including propri-
May 2004
BLUETOOTH™ SINGLE CHIP
PRELIMINARY DATA
Figure 1. Package
TFBGA84
Table 1. Order Codes
Part Number
STLC2500
Package
TFBGA84
etary extensions)
– HCI proprietary commands (e.g. peripherals
control)
– Single HCI command for patch/upgrade download
■ Single power supply with internal regulators for
core voltage generation
■ Supports 1.65 to 2.85 Volts IO systems
■ Total number of external components limited to 7
(6 decoupling capacitors and 1 filter) thanks to:
– Fully integrated synthesizer (VCO and loop filter)
– Integrated antenna switch
– Low IF receiver
■ Auto calibration (VCO, Filters)
■ No need for calibration of the RF part
■ Timer and watchdog
■ Power class 2 compatible
■ Ultra low power architecture with 3 different low
power levels:
– Sleep Mode
– Deep Sleep Mode
– Complete Power Down Mode
■ Software Initiated Low Power Mode
■ Dual Wake-up mechanism: initiated either by
the Host or by the Bluetooth device
■ Standard TFBGA-84 pins package
2 DESCRIPTION
The STLC2500 is a single chip ROM-based Blue-
tooth solution implemented in 0.13 m ultra low
power, low leakage CMOS technology for applica-
tions requiring integration up to HCI level. Patch
RAM is available enabling multiple patches/up-
grades.
The STLC2500's main interfaces are UART for
HCI transport, PCM for voice and GPIOs for con-
trol purposes. The Radio is designed for the single
chip requirement and for drastic power consump-
tion reduction.
REV. 1
1/23
This is preliminary information on a new product now in development. Details are subject to change without notice.
1 page  
STLC2500
5 PINOUT
5.1 Pin out bottom view
10 9 8 7 6
ANA_1
ABUS_
QP_IP
ABUS_
IN_QN
VSS_RF
RFN
A
54321
RFP
VSS_RF VDD_HV VSS_ANA VSS_DIG
ABUS_
VSS_ANA VSS_ANA QN_IN
B
ABUS_
IP_QP
VSS_ ANA VDD_RF
ANA_2 VSS_ANA VDD_DIG JTAG_TDO
ANA_3
VDD_HV VSS_ANA VSS_ANA
VDD_T
VSS_ANA VSS_ANA VDD_DIG
JTAG_
NTRST
JTAG_TDI
C
VDD_HV ANA_4 VSS_ANA
D
VDD_DSM VSS_ANA VSS_ANA
E
VDD_N VDD_HV VSS_ANA
F
VSS_DIG JTAG_TCK JTAG_TMS
VSS_DIG PCM_SYNC PCM_CLK
VDD_IO_A PCM_A PCM_B
VDD_CL VSS_ANA VDD_CLD
VSS_DIG VDD_IO_A VDD_IO_A
G
CONFIG
RF_CLK_IN VDD_CLD VSS_DIG VSS_DIG VSS_DIG VSS_DIG VSS_DIG
_R
CONFIG
_CLK
CONFIG
_JS
H
VDD_DIG GPIO_2 GPIO_0
UART_
RXD
UART_
CTS
HOST_
WAKEUP
CONFIG
_RF
BT_
WAKEUP
VDD_DIG
CONFIG
_M
J
AF_PRG GPIO_3 PGIO_1
UART_
TXD
UART_
RTS
LP_CLK VDD_IO_B RESETN
VDD_D
VDD_HV
K
5.2 Pin Description and Assignment
Table 13 shows the pin list of the STLC2500. The column "PU/PD" shows the pads implementing a pull-
down/up. The column "DIR" describes the pin directions:
– I for Inputs
– O for Outputs
– I/O for Input/Output
– O/t for tri-state outputs
The column Reset and Default show the state of the pins in reset and the default value after reset. For the
output pin the default drive capability is 2 mA.
Table 13. STLC2500 pin list (Functional and Supply)
Name
Pin #
Description
Clock and Reset pins
RESETN
K03
RF_CLK_IN
H10
LP_CLK
K05
Global reset - active low
Reference clock input
Low power clock input
DIR
Reset
Default
after reset
VDD_
IO_x
I
Input
Input
A
I
Input
Input
(3)
I
Input
Input
B
5/23
5 Page 
STLC2500
Technical perspective - Faster Connection
The Faster Inquiry functionality is based on a removed/shortened random back off and also a new Inter-
laced Inquiry Scan scheme.
The Faster Page functionality is based on Interlaced Page Scan.
6.5.4 V1.2 detailed functionality - Quality of Service
User Perspective - Quality of Service
Small changes to the BT1.1 spec regarding Quality of Service make a large difference.
Allowing all QoS parameters to be communicated over HCI to the link manager enables efficient band-
width management. Here after a short list of user perspectives:
1) Flush timeout: enables time-bounded traffic such as video streaming to become more robust when the
channel degrades. It sets the maximum delay of an L2CAP frame. It does not enable multiple streams
in one piconet, or heavy data transfer at the same time.
2) Simple latency control: allows the Host to set the poll interval. This provides support for HID devices
mixed with other traffic in the piconet.
6.6 Processor and memory
– ARM7TDMI
– On chip RAM, including provision for patches
– On chip ROM, preloaded with SW up to HCI
7 GENERAL SPECIFICATION
All the provided values are specified over the operational conditions (VDD and temperature) according to
the Bluetooth 1.1 and 1.2 specifications unless otherwise specified.
7.1 Receiver
To be compliant with the Bluetooth norm, an external RF filter is required to provide minimum -17dB of
attenuation in the band: 30MHz - 2000MHz and 3000MHz - 12.75GHz. All specifications below are given
at pin level and over temperature unless otherwise specified.
Table 16. Receiver Parameters (Tamb = 25°C, VDD_HV = 2.75V, parameters are given at device pin.)
Symbol
Parameter
RFin
Input frequency range
RXsens
Receiver Sensitivity
(Clean transmitter)
RXmax
Maximum useable input signal
level
Receiver interferer performance @BER 0.1%
C/Ico-channel Co-channel interference
C/I1MHz Adjacent (±1MHz) interference
C/I+2MHz Adjacent (+2MHz) interference
C/I-2MHz Adjacent (-2MHz) interference
Test Condition
@ BER 0.1%
@ BER 0.1%
@ Input signal
strength = -60dBm
@ Input signal
strength = -60dBm
@ Input signal
strength = -60dBm
@ Input signal
strength = -67dBm
Min.
2402
Typ.
-85
Max.
2480
Unit
MHz
dBm
+15 dBm
9 dB
-2 dB
-35 dB
-25 dB
11/23
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| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet STLC2500.PDF ] | |
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