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PDF MT28C3214P2FL Data sheet ( Hoja de datos )
| Número de pieza | MT28C3214P2FL | |
| Descripción | FLASH AND SRAM COMBO MEMORY | |
| Fabricantes | Micron Technology | |
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FLASH AND SRAM
COMBO MEMORY
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
MT28C3214P2FL
MT28C3214P2NFL
Low Voltage, Extended Temperature
FEATURES
• Flexible dual-bank architecture
• Support for true concurrent operations with no
latency:
Read bank b during program bank a and vice versa
Read bank b during erase bank a and vice versa
• Organization: 2,048K x 16 (Flash)
256K x 16 (SRAM)
• Basic configuration:
Flash
Bank a (4Mb Flash for data storage)
– Eight 4K-word parameter blocks
– Seven 32K-word blocks
Bank b (28Mb Flash for program storage)
– Fifty-six 32K-word main blocks
SRAM
4Mb SRAM for data storage
– 256K-words
• F_VCC, VCCQ, F_VPP, S_VCC voltages1
1.65V (MIN)/1.95V (MAX) F_VCC read voltage or
1.80V (MIN)/2.20V (MAX) F_VCC read voltage
1.65V (MIN)/1.95V (MAX) S_VCC read voltage or
1.80V (MIN)/2.20V (MAX) S_VCC read voltage
1.65V (MIN)/1.95V (MAX) VCCQ or
1.80V (MIN)/2.20V (MAX) VCCQ
1.80V (TYP) F_VPP (in-system PROGRAM/ERASE)
0.0V (MIN)/2.20V (MAX) F_VPP (in-system
PROGRAM/ERASE)2
12V ±5% (HV) F_VPP (production programming
compatibility)
• Asynchronous access time1
Flash access time: 100ns or 110ns @ 1.65V F_VCC
SRAM access time: 100ns @ 1.65V S_VCC
• Page Mode read access1
Interpage read access: 100ns/110ns @ 1.65V F_VCC
Intrapage read access: 35ns/45ns @ 1.65V F_VCC
• Low power consumption
• Enhanced suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
• Read/Write SRAM during program/erase of Flash
• Dual 64-bit chip protection registers for security
purposes
• PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
BALL ASSIGNMENT
66-Ball FBGA (Top View)
1 2 3 4 5 6 7 8 9 10 11 12
A NC
NC A20 A11 A15 A14 A13 A12 F_VSS VccQ NC
NC
B A16 A8 A10 A9 DQ15 S_WE# DQ14 DQ7
C F_WE# NC
DQ13 DQ6 DQ4 DQ5
D S_VSS F_RP#
DQ12 S_CE2 S_VCC F_VCC
E
F_WP# F_VPP A19 DQ11
DQ10 DQ2 DQ3
F
S_LB# S_UB# S_OE#
DQ9 DQ8 DQ0 DQ1
G A18 A17 A7 A6 A3 A2 A1 S_CE1#
H NC NC F_VCC A5 A4 A0 F_CE# F_VSS F_OE# NC NC NC
Top View
(Ball Down)
• Cross-compatible command set support
Extended command set
Common flash interface (CFI) compliant
NOTE:
1. These specifications are guaranteed for operation
within either one of two voltage ranges, 1.65V–1.95V
or 1.80V–2.20V. Use only one of the two voltage
ranges for PROGRAM and ERASE operations.
2. MT28C3214P2NFL only.
OPTIONS
MARKING
• Timing
100ns
-10
110ns
-11
• Boot Block
Top T
Bottom
B
• VPP1 Range
0.9V–2.2V
None
0.0V–2.2V
N
• Operating Temperature Range
Commercial Temperature (0oC to +70oC) None
Extended Temperature (-40oC to +85oC) ET
• Package
66-ball FBGA (8 x 8 grid)
FL
Part Number Example:
MT28C3214P2FL-10 TET
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02
1
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
1 page  
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
BALL DESCRIPTIONS
66-BALL FBGA
NUMBERS
A3, A4, A5, A6,
A7, A8, B3, B4,
B5, B6, E5, G3,
G4, G5, G6, G7,
G8, G9, H4, H5,
H6
H7
SYMBOL
A0–A20
F_CE#
TYPE
Input
Input
H9 F_OE# Input
C3 F_WE# Input
D4 F_RP# Input
E3 F_WP# Input
G10 S_CE1# Input
D8 S_CE2 Input
F5 S_OE# Input
B8 S_WE# Input
F3 S_LB# Input
F4 S_UB# Input
B7, B9, B10, DQ0–DQ15 Input/
C7, C8, C9,
Output
C10, D7, E6,
E8, E9, E10,
F7, F8, F9, F10
DESCRIPTION
Address Inputs: Inputs for the addresses during READ and WRITE
operations. Addresses are internally latched during READ and WRITE
cycles. Flash: A0–A20; SRAM: A0–A17.
Flash Chip Enable: Activates the device when LOW. When CE# is HIGH,
the device is disabled and goes into standby power mode.
Flash Output Enable: Enables Flash output buffers when LOW. When
F_OE# is HIGH, the output buffers are disabled.
Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle.
F_WE# is active LOW.
Reset. When F_RP# is a logic LOW, the device is in reset, which drives
the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH,
the device is in standard operation. When F_RP# transitions from logic
LOW to logic HIGH, the device resets all blocks to locked and defaults to
the read array mode.
Flash Write Protect. Controls the lock down function of the flexible
locking feature.
SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level
deselects the SRAM and reduces the power consumption to standby
levels.
SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level
deselects the SRAM and reduces the power consumption to standby
levels.
SRAM Output Enable: Enables SRAM output buffers when LOW. When
S_OE# is HIGH, the output buffers are disabled.
SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle.
S_WE# is active LOW.
SRAM Lower Byte: When LOW, it selects the SRAM address lower byte
(DQ0–DQ7).
SRAM Upper Byte: When LOW, it selects the SRAM address upper byte
(DQ8–DQ15).
Data Inputs/Outputs: Input array data on the second CE# and WE#
cycle during PROGRAM command. Input commands to the command
user interface when CE# and WE# are active. Output data when CE#
and OE# are active.
(continued on next page)
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
5 Page 
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
order I/O signals (DQ0–DQ7) need to be interpreted.
Address lines select the status register pertinent to the
selected memory partition.
Register data is updated and latched on the rising
edge of F_OE# or F_CE#, whichever occurs first. The
latest falling edge of either of these two signals up-
dates the latch within a given READ cycle. Latching the
data prevents errors from occurring if the register input
changes during a status register read.
The status register provides the internal state of the
WSM to the external microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 8 defines the sta-
tus register bits.
After monitoring the status register during a
PROGRAM/ERASE operation, the data appearing on
DQ0–DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.
COMMAND STATE MACHINE OPERATIONS
The CSM decodes instructions for the commands
listed in Table 4. The 8-bit command code is input to
the device on DQ0–DQ7 (see Table 5 for command
definitions). During a PROGRAM or ERASE cycle, the
CSM informs the WSM that a PROGRAM or ERASE cycle
has been requested.
During a PROGRAM cycle, the WSM controls the
program sequences and the CSM responds to a PRO-
GRAM SUSPEND command only.
During an ERASE cycle, the CSM responds to an
ERASE SUSPEND command only. When the WSM has
completed its task, the WSMS bit (SR7) is set to a logic
HIGH level and the CSM responds to the full command
set. The CSM stays in the current command state until
the microprocessor issues another command.
The WSM successfully initiates an ERASE or PRO-
GRAM operation only when VPP is within its correct volt-
age range.
Table 5
Command Definitions
COMMAND
READARRAY
READ PROTECTION CONFIGURATION REGISTER
READ STATUS REGISTER
CLEAR STATUS REGISTER
READ QUERY
BLOCK ERASE SETUP
PROGRAM SETUP/ALTERNATE PROGRAM SETUP
PROGRAM/ERASE SUSPEND
PROGRAM/ERASE RESUME – ERASE CONFIRM
LOCK BLOCK
UNLOCK BLOCK
LOCK DOWN BLOCK
PROTECTION REGISTER PROGRAM
PROTECTION REGISTER LOCK
FIRST BUS CYCLE
OPERATION ADDRESS DATA
WRITE
WA
FFh
WRITE
IA
90h
WRITE
BA
70h
WRITE
BA
50h
WRITE
QA
98h
WRITE
BA
20h
WRITE
WA 40h/10h
WRITE
BA
B0h
WRITE
BA
D0h
WRITE
BA
60h
WRITE
BA
60h
WRITE
BA
60h
WRITE
PA
C0h
WRITE
LPA
C0h
SECOND BUS CYCLE
OPERATION ADDRESS DATA
READ
READ
IA
BA
ID
SRD
READ
WRITE
WRITE
QA
BA
WA
QD
D0h
WD
WRITE
BA
01h
WRITE
BA
D0h
WRITE
BA
2Fh
WRITE
PA
PD
WRITE LPA FFFDh
NOTE: 1. WA: Word address of memory location to be written, or read
2. IA: Identification code address
3. BA: Address within the block
4. ID: Identification code data
5. SRD: Data read from the status register
6. QA: Query code address
7. QD: Query code data
8. WD: Data to be written at the location WA
9. PA: Protection register address
10. LPA: Lock protection register address
11. PD: Protection register data
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
11 Page | ||
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| PDF Descargar | [ Datasheet MT28C3214P2FL.PDF ] | |
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