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PDF ICS9250-10 Data sheet ( Hoja de datos )
| Número de pieza | ICS9250-10 | |
| Descripción | Frequency Timing Generator for Pentium II Systems | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS9250-10 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS9250 - 10
Preliminary Product Preview
Frequency Timing Generator for Pentium II Systems
General Description
The ICS9250-10 is a single chip clock for Intel Pentium II.
It provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board
design iterations or costly shielding. The ICS9250-10
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Block Diagram
Features
Generates the following system clocks:
- 3 CPU (2.5V) 66.6/100 MHz (up to 133MHz through
I2C selection)
- 9 SDRAM (3.3V) up to 133MHz
- 8 PCI (3.3 V) @33.3MHz
- 2 IOAPIC (2.5V) @16.67 or 33.3MHz
- 2 Hublink clocks (3.3 V) @ 66.6 MHz
- 2 USB (3.3V) @ 48 MHz ( Non spread spectrum)
- 1 REF (3.3V) @ 14.318 MHz
Supports spread spectrum modulation ,
down spread 0 to -0.5%
I2C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Pin Configuration
Pentium II is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9250-10 Rev J 6/15/99
56-Pin 300 mil SSOP
*60K ohm pull-up to VDD on indicated inputs.
Power Groups
VDD0, GND0 = REF & Crystal
VDD1, GND1 = 3V66 [1:0]
VDD2, GND2 = PCICLK[7:0]
VDD3, GND3 = PLL core
VDD4, GND4 = 48MHz [1:0]
VDD5, GND5 = SDRAM_F, SDRAM [7:0]
VDDL0, GNDL0 = CPUCLK [2:0]
VDDL1, GNDL1 = IOAPIC [1:0]
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
1 page  
ICS9250 - 10
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
Dummy Command Code
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Stop Bit
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
ICS (Slave/Receiver)
ACK
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
5
5 Page 
ICS9250 - 10
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
Output Impedance
RDSP4B1 VO = VDD*(0.5)
Output Impedance RDSN4B1 VO = VDD*(0.5)
Output High Voltage VOH4\B IOH = -5.5 mA
Output Low Voltage VOL4B IOL = 9.0 mA
Output High Current
IOH4B VOH@ min = 1.0 V, VOH@ MAX = 2.375 V
Output Low Current
Rise Time
IOL4B
tr4B1
VOL@ MIN = 1.2 V, VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
Fall Time
tf4B1 VOH = 2.0 V, VOL = 0.4 V
Duty Cycle
dt4B1 VT = 1.25 V
Jitter
Skew
tjcyc-cyc
Tsk41
VT = 1.25 V
1Guarenteed by design, not 100% tested in production.
MIN TYP MAX UNITS
9 30 Ω
9 30 Ω
2V
0.4 V
-27 -27 mA
27 30 mA
0.4 1.6 ns
0.4 1.6 ns
45 55 %
500 ps
250 ps
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output Impedance
Output Impedance
RDSP31
RDSN31
VO = VDD*(0.5)
VO = VDD*(0.5)
10 24 Ω
10 24 Ω
Output High Voltage VOH3 IOH = -1 mA
2.4 V
Output Low Voltage
VOL3 IOL = 1 mA
0.4 V
Output High Current
IOH3 VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
-54
-46 mA
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
IOL3
Tr31
Tf31
Dt31
Tsk31
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
54 53 mA
0.4 1.6 ns
0.4 1.6 ns
45 55 %
250 ps
Jitter
tjcyc-cyc VT = 1.5 V
250 ps
1Guarenteed by design, not 100% tested in production.
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS9250-10.PDF ] | |
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