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PDF ICS9250-25 Data sheet ( Hoja de datos )
| Número de pieza | ICS9250-25 | |
| Descripción | Frequency Generator & Integrated Buffers for Celeron & PII/III | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS9250-25 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS9250-25
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E and Solano type chipset
Output Features:
• 2 - CPUs @ 2.5V, up to 153.33MHz.
• 13 - SDRAM @ 3.3V, up to 153.33MHz.
• 3 - 3V66 @ 3.3V, 2x PCI MHz.
• 8 - PCI @3.3V.
• 1 - 48MHz, @3.3V fixed.
• 1 - 24MHz @ 3.3V
• 1 - REF @3.3V, 14.318MHz.
Features:
• Up to 153.33MHz frequency support
• Support power management through PD#.
• Spread spectrum for EMI control (± 0.25%)
center spread.
• Uses external 14.318MHz crystal
• FS pins for frequency select
Key Specifications:
• CPU Output Jitter: <250ps
• IOAPIC Output Jitter: <500ps
• 48MHz, 3V66, PCI Output Jitter: <500ps
• Ref Output Jitter. <1000ps
• CPU Output Skew: <175ps
• PCI Output Skew: <500ps
• 3V66 Output Skew <175ps
• For group skew timing, please refer to the
Group Timing Relationship Table.
Pin Configuration
VDDREF
X1
X2
GNDREF
GND3V66
3V66-0
3V66-1
3V66-2
VDD3V66
VDDPCI
1*FS0/PCICLK0
1*FS1/PCICLK1
PCICLK2
GNDPCI
PCICLK3
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PD#
SCLK
SDATA
VDDSDR
SDRAM11
SDRAM10
GNDSDR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 REF0/FS4*1
55 VDDLAPIC
54 IOAPIC
53 VDDLCPU
52 CPUCLK0
51 CPUCLK1
50 GNDLCPU
49 GNDSDR
48 SDRAM0
47 SDRAM1
46 SDRAM2
45 VDDSDR
44 SDRAM3
43 SDRAM4
42 SDRAM5
41 GNDSDR
40 SDRAM6
39 SDRAM7
38 SDRAM_F
37 VDDSDR
36 GND48
35 24MHz/FS2*
34 48MHz/FS3*1
33 VDD48
32 VDDSDR
31 SDRAM8
30 SDRAM9
29 GNDSDR
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
FS[4:0]
PD#
SDATA
SCLK
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
SDRAM
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
48MHz
24MHz
REF0
2 CPUCLK [1:0]
12 SDRAM [11:0]
SDRAM_F
IOAPIC
PCICLK [7:0]
8
3V66 [2:0]
3
9250-25 Rev A 10/03/00
Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new products
in the sampling or preproduction phase of development. Characteristic
data and other specifications are subject to change without notice.
1 page  
ICS9250-25
Preliminary Product Preview
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
-X
-X
-X
35 1
-1
34 1
-1
38 1
Byte 3: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
20 1
19 1
17 1
16 1
15 1
13 1
12 1
11 1
Description
FS3#
FS0#
FS2#
24MHz
(Reserved)
48MHz
(Reserved)
SDRAM_F
Description
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
39 1
40 1
42 1
43 1
44 1
46 1
47 1
48 1
Byte 4: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
81
61
71
-X
54 1
-X
51 1
52 1
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Description
3V66_2
3V66_0
3V66_1
FS4#
IOAPIC
FS1#
CPUCLK1
CPUCLK0
Byte 5: Control Register
(1 = enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
-1
-1
-1
-1
26 1
27 1
30 1
31 1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Bit Pin# PWD
Description
Bit7 -
0 Reserved (Note)
Bit6 -
0 Reserved (Note)
Bit5 -
0 Reserved (Note)
Bit4 -
0 Reserved (Note)
Bit3 -
0 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
0 Reserved (Note)
Note: Dont write into this register, writing into this register
can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
Third party brands and names are the property of their respective owners.
5
5 Page 
ICS9250-25
Preliminary Product Preview
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS9250-25
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage) that
is present on these pins at this time is read and stored into a 5-
bit internal data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In this
mode the pins produce the specified buffered clocks to external
loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
Programming
Header
Via to Gnd
Via to
VDD
2K W
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS9250-25.PDF ] | |
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