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PDF MB8117800A Data sheet ( Hoja de datos )
| Número de pieza | MB8117800A | |
| Descripción | 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM | |
| Fabricantes | ETC | |
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FUJITSU SEMICONDUCTOR
DATA SHEET
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DS05-10167-3E
MEMORY
CMOS
2 M × 8 BIT
FAST PAGE MODE DYNAMIC RAM
MB8117800A-60/-70
CMOS 2,097,152 × 8 Bit Fast Page Mode Dynamic RAM
s DESCRIPTION
The Fujitsu MB8117800A is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory
cells accessible in 8-bit increments. The MB8117800A features a “fast page” mode of operation whereby high-
speed random access of up to 1,024-bits of data within the same row can be selected. The MB8117800A DRAM
is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory
applications where very low power dissipation and high bandwidth are basic requirements of the design. Since
the standby current of the MB8117800A is very small, the device can be used as a non-volatile memory in
equipment that uses batteries for primary and/or auxiliary power.
The MB8117800A is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon and two-
layer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the
possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for
the MB8117800A are not critical and all inputs are TTL compatible.
s PRODUCT LINE & FEATURES
Parameter
RAS Access Time
Random Cycle Time
Address Access Time
CAS Access Time
Hyper Page Mode Cycle Time
Low Power
Dissipation
Operating Current
Standby Current
MB8117800A-60
MB8117800A-70
60 ns max.
70 ns max.
110 ns min.
130 ns min.
30 ns max.
35 ns max.
15 ns max.
17 ns max.
40 ns min.
45 ns min.
715 mW max.
660 mW max.
11 mW max. (TTL level) / 5.5 mW max. (CMOS level)
• 2,097,152 words × 8 bit organization
• Silicon gate, CMOS, Advanced Capacitor Cell
• All input and output are TTL compatible
• 2048 refresh cycles every 32.8ms
• Self refresh function
• Early write or OE controlled write capability
• RAS-only, CAS-before-RAS, or Hidden
Refresh
• Fast Page Mode, Read-Modify-Write
capability
• On chip substrate bias generator for high
performance
1
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MB8117800A-60/-70
s FUNCTIONAL TRUTH TABLE
Clock Input
Operation Mode
RAS CAS WE OE
Standby
HHXX
Read Cycle
L LHL
Write Cycle
(Early Write)
LLLX
Read-Modify-
Write Cycle
L L H→L L→H
RAS-only
Refresh Cycle
LHXX
CAS-before-
RAS Refresh
Cycle
L L XX
Hidden Refresh
Cycle
H→L
L
H→X
L
Address
Input Data
Refresh
Row Column Input Output
Note
— — — High-Z —
Valid Valid — Valid Yes* tRCS ≥ tRCS (min)
Valid Valid Valid High-Z Yes* tWCS ≥ tWCS (min)
Valid Valid Valid Valid Yes*
Valid
—
— High-Z Yes
— — — High-Z Yes tCSR ≥ tCSR (min)
—
—
—
Valid
Yes
Previous data is
kept.
X; “H” or “L”
*; It is impossible in Fast Page Mode.
s FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty-one input bits are required to decode any eight of 16,777,216 cell addresses in the memory matrix.
Since only eleven address bits (A0 to A10) are available, the row and column inputs are separately strobed by
RAS and CAS as shown in Figure 1. First, eleven row address bits are input on pins A0-through-A10 and latched
with the row address strobe (RAS) then, ten column address bits are input and latched with the column address
strobe (CAS). Both row and column addresses must be stable on or before the falling edge of RAS and CAS,
respectively. The address latches are of the flow-through type; thus, address information appearing after tRAH
(min) + tT is automatically treated as the column address.
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUTS
Input data is written into memory in either of three basic ways-an early write cycle, an OE (delayed) write cycle,
and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch
strobe. In an early write cycle, the input data (DQ1-DQ8) is strobed by CAS and the setup/hold times are referenced
to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes Low after
CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal.
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MB8117800A-60/-70
Notes: *1. Referenced to VSS.
*2. ICC depends on the output load conditions and cycle rates; The specified values are obtained with the
output open. ICC depends on the number of address change as RAS = VIL, CAS = VIH and VIL > –0.3 V.
ICC1, ICC3, ICC4 and ICC5 are specified at one time of address change during RAS = VIL and CAS = VIH. ICC2
is specified during RAS = VIH and VIL > –0.3 V.
*3. An initial pause (RAS = CAS = VIH) of 200 µs is required after power-up followed by any eight RAS-only cycles
before proper device operation is achieved. In case of using internal refresh counter, a minimum of eight
CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
*4. AC characteristics assume tT = 5 ns.
*5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also transition times are
measured between VIH (min) and VIL (max).
*6. Assumes that tRCD ≤ tRCD (max), tRAD ≤ tRAD (max). If tRCD is greater than the maximum recommended value
shown in this table, tRAC will be increased by the amount that tRCD exceeds the value shown. Refer to Fig.2 and 3.
*7. If tRCD ≥ tRCD (max), tRAD ≥ tRAD (max), and tASC ≥ tAA – tCAC – tT, access time is tCAC.
*8. If tRAD ≥ tRAD (max) and tASC ≤ tAA – tCAC – tT, access time is tAA.
*9. Measured with a load equivalent to two TTL loads and 100 pF.
*10. tOFF and tOEZ is specified that output buffer change to high impedance state.
*11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, access time is controlled
exclusively by tCAC or tAA.
*12. tRCD (min) = tRAH (min) + 2 tT + tASC (min).
*13. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, access time is controlled
exclusively by tCAC or tAA.
*14. Either tRRH or tRCH must be satisfied for a read cycle.
*15. tWCS is specified as a reference point only. If tWCS ≥ tWCS (min) the data output pin will remain High-Z state
through entire cycle.
*16. Assumes that tWCS < tWCS (min).
*17. Either tDZC or tDZO must be satisfied.
*18. tCPA is access time from the selection of a new column address (that is caused by changing CAS from “L” to
“H”). Therefore, if tCP is long, tCPA is longer than tCPA (max).
*19. Assumes that CAS-before-RAS refresh.
*20. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristic only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and DOUT pin
will maintain high impedance state through-out the entire cycle. If tCWD ≥ tCWD (min), tRWD ≥ tRWD (min),
tAWD ≥ tAWD (min) and tCPWD ≥ tCPWD (min), the cycle is a read-modify-write cycle and data from the selected
cell will appear at the DOUT pin. If neither of the above conditions is satisfied, the cycle is a delayed write cycle
and invalid data will appear the DOUT pin, and write operation can be executed by satisfying tRWL, tCWL, and tRAL
specifications.
11
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