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PDF LT1721 Data sheet ( Hoja de datos )
| Número de pieza | LT1721 | |
| Descripción | Dual/Quad/ 4.5ns/ Single Supply 3V/5V Comparators with Rail-to-Rail Outputs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LT1721 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
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LT1720/LT1721
FEATURES
Dual/Quad, 4.5ns, Single
Supply 3V/5V Comparators
with Rail-to-Rail Outputs
DESCRIPTION
n UltraFast: 4.5ns at 20mV Overdrive
7ns at 5mV Overdrive
n Low Power: 4mA per Comparator
n Optimized for 3V and 5V Operation
n Pinout Optimized for High Speed Ease of Use
n Input Voltage Range Extends 100mV
Below Negative Rail
n TTL/CMOS Compatible Rail-to-Rail Outputs
n Internal Hysteresis with Specified Limits
n Low Dynamic Current Drain; 15μA/(V-MHz),
Dominated by Load In Most Circuits
n Tiny 3mm × 3mm × 0.75mm DFN Package (LT1720)
APPLICATIONS
n High Speed Differential Line Receiver
n Crystal Oscillator Circuits
n Window Comparators
n Threshold Detectors/Discriminators
n Pulse Stretchers
n Zero-Crossing Detectors
n High Speed Sampling Circuits
The LT®1720/LT1721 are UltraFastTM dual/quad compara-
tors optimized for single supply operation, with a supply
voltage range of 2.7V to 6V. The input voltage range extends
from 100mV below ground to 1.2V below the supply volt-
age. Internal hysteresis makes the LT1720/LT1721 easy to
use even with slow moving input signals. The rail-to-rail
outputs directly interface to TTL and CMOS. Alternatively,
the symmetric output drive can be harnessed for analog
applications or for easy translation to other single supply
logic levels.
The LT1720 is available in three 8-pin packages; three pins
per comparator plus power and ground. In addition to SO
and MSOP packages, a 3mm × 3mm low profile (0.8mm)
dual fine pitch leadless package (DFN) is available for space
limited applications. The LT1721 is available in the 16-pin
SSOP and S packages.
The pinouts of the LT1720/LT1721 minimize parasitic
effects by placing the most sensitive inputs (inverting)
away from the outputs, shielded by the power rails. The
LT1720/LT1721 are ideal for systems where small size and
low power are paramount.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. UltaFast is
a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
TYPICAL APPLICATION
2.7V to 6V Crystal Oscillator with TTL/CMOS Output
2.7V TO 6V
2k
1MHz TO 10MHz
CRYSTAL (AT-CUT)
220Ω
620Ω
GROUND
+ CASE
C1
1/2 LT1720
–
2k
0.1μF
1.8k
OUTPUT
17201 TA01
Propagation Delay vs Overdrive
8
7
6
RISING EDGE
(tPDLH)
5
25°C
VSTEP = 100mV
VCC = 5V
CLOAD = 10pF
4
FALLING EDGE
3 (tPDHL)
2
1
0
0 10 20 30 40 50
OVERDRIVE (mV)
17201 TA02
17201fc
1
1 page  
TYPICAL PERFORMANCE CHARACTERISTICS
Input Current
vs Differential Input Voltage
2
25°C
1 VCC = 5V
0
–1
–2
–3
–4
–5
–6
–7
–5 –4 –3 –2 –1 0 1 2 3 4
DIFFERENTIAL INPUT VOLTAGE (V)
5
17201 G04
Propagation Delay
vs Load Capacitance
9
25°C
8 VSTEP = 100mV
OVERDRIVE = 20mV
7 VCC = 5V
RISING EDGE
(tPDLH)
6
5 FALLING EDGE
(tPDHL)
4
3
2
1
0
0 10 20 30 40 50
OUTPUT LOAD CAPACITANCE (pF)
17201 G07
Output Low Voltage
vs Load Current
0.5
VCC = 5V
VCM = 1V
VIN = –15mV
0.4 125°C
VCC = 2.7V
125°C
0.3
–55°C
25°C
0.2
0.1
0
4 8 12 16
OUTPUT SINK CURRENT (mA)
20
17201 G10
Quiescent Supply Current
vs Temperature
6.0
5.5
5.0
4.5
VCC = 5V
4.0
VCC = 3V
3.5
3.0
2.5
2.0
–50 –25
0 25 50 75
TEMPERATURE (˚C)
100 125
17201 G05
Propagation Delay
vs Temperature
8.0
7.5
VCC = 3V
7.0
tPDLH
VCM = 1V
VSTEP = 100mV
CLOAD = 10pF
6.5 VCC = 5V
6.0 OVERDRIVE = 5mV
5.5
VCC = 5V
5.0
OVERDRIVE = 20mV
4.5
VCC = 3V
4.0
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C)
17201 G08
Output High Voltage
vs Load Current
0.0
125°C
–0.2
VCC = 5V
VCM = 1V
VIN = 15mV
–55°C
–0.4 25°C
–0.6
–0.8
–1.0
0
25°C
VCC = 2.7V
4 8 12 16
OUTPUT SOURCE CURRENT (mA)
20
17201 G11
LT1720/LT1721
Quiescent Supply Current
vs Supply Voltage
7
6 125°C
5
25°C
4
3 –55°C
2
1
0
01 2 34 5 6 7
SUPPLY VOLTAGE (V)
17201 G06
Propagation Delay
vs Supply Voltage
5.0
25°C
VSTEP = 100mV
OVERDRIVE = 20mV
CLOAD = 10pF
RISING EDGE
4.5 (tPDLH)
FALLING EDGE
(tPDHL)
4.0
2.5 3.0
3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
5.5 6.0
17201 G09
Supply Current vs Frequency
10
25°C
9 VCC = 5V
8
CLOAD = 20pF
7
6
NO LOAD
5
4
3
0 10 20 30 40
FREQUENCY (MHz)
17201 G12
17201fc
5
5 Page 
LT1720/LT1721
APPLICATIONS INFORMATION
Interfacing the LT1720/LT1721 to ECL
The LT1720/LT1721 comparators can be used in high
speed applications where Emitter-Coupled Logic (ECL) is
deployed. To interface the outputs of the LT1720/LT1721
to ECL logic inputs, standard TTL/CMOS to ECL level
translators such as the 10H124, 10H424 and 100124
can be used. These components come at a cost of a few
nanoseconds additional delay as well as supply currents
of 50mA or more, and are only available in quads. A faster,
simpler and lower power translator can be constructed
with resistors as shown in Figure 5.
Figure 5a shows the standard TTL to Positive ECL (PECL)
resistive level translator. This translator cannot be used for
the LT1720/LT1721, or with CMOS logic, because it depends
on the 820Ω resistor to limit the output swing (VOH) of
the all-NPN TTL gate with its so-called totem-pole output.
The LT1720/LT1721 are fabricated in a complementary
bipolar process and their output stage has a PNP driver
that pulls the output nearly all the way to the supply rail,
even when sourcing 10mA.
Figure 5b shows a three resistor level translator for interfac-
ing the LT1720/LT1721 to ECL running off the same supply
rail. No pull-down on the output of the LT1720/LT1721
is needed, but pull-down R3 limits the VIH seen by the
PECL gate. This is needed because ECL inputs have both
a minimum and maximum VIH specification for proper
operation. Resistor values are given for both ECL interface
types; in both cases it is assumed that the LT1720/LT1721
operates from the same supply rail.
Figure 5c shows the case of translating to PECL from an
LT1720/LT1721 powered by a 3V supply rail. Again, resis-
tor values are given for both ECL interface types. This time
four resistors are needed, although with 10KH/E, R3 is not
needed. In that case, the circuit resembles the standard TTL
translator of Figure 5a, but the function of the new resistor,
R4, is much different. R4 loads the LT1720/LT1721 output
when high so that the current flowing through R1 doesn’t
forward bias the LT1720/LT1721’s internal ESD clamp diode.
Although this diode can handle 20mA without damage,
normal operation and performance of the output stage can
be impaired above 100μA of forward current. R4 prevents
this with the minimum additional power dissipation.
Finally, Figure 5d shows the case of driving standard, nega-
tive-rail, ECL with the LT1720/LT1721. Resistor values are
given for both ECL interface types and for both a 5V and 3V
LT1720/LT1721 supply rail. Again, a fourth resistor, R4 is
needed to prevent the low state current from flowing out of
the LT1720/LT1721, turning on the internal ESD/substrate
diodes. Not only can the output stage functionality and
speed suffer, but in this case the substrate is common to
all the comparators in the LT1720/LT1721, so operation
of the other comparator(s) in the same package could
also be affected. Resistor R4 again prevents this with the
minimum additional power dissipation.
For all the dividers shown, the output impedance is about
110Ω. This makes these fast, less than a nanosecond,
with most layouts. Avoid the temptation to use speedup
capacitors. Not only can they foul up the operation of
the ECL gate because of overshoots, they can damage
the ECL inputs, particularly during power-up of separate
supply configurations.
The level translator designs assume one gate load. Multiple
gates can have significant IIH loading, and the transmis-
sion line routing and termination issues also make this
case difficult.
ECL, and particularly PECL, is valuable technology for high
speed system design, but it must be used with care. With
less than a volt of swing, the noise margins need to be
evaluated carefully. Note that there is some degradation of
noise margin due to the ±5% resistor selections shown.
With 10KH/E, there is no temperature compensation of the
logic levels, whereas the LT1720/LT1721 and the circuits
shown give levels that are stable with temperature. This
will degrade the noise margin over temperature. In some
configurations it is possible to add compensation with
diode or transistor junctions in series with the resistors
of these networks.
For more information on ECL design, refer to the ECLiPS
data book (DL140), the 10KH system design handbook
(HB205) and PECL design (AN1406), all from ON
Semiconductor (www.onsemi.com).
17201fc
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LT1721.PDF ] | |
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