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PDF AMD29F010B Data sheet ( Hoja de datos )
| Número de pieza | AMD29F010B | |
| Descripción | 1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only / Uniform Sector Flash Memory | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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Am29F010B
1 Megabit (128 K x 8-bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation
— 5.0 V ± 10% for read, erase, and program operations
— Simplifies system-level power requirements
s Manufactured on 0.32 µm process technology
— Compatible with Am29F010 and Am29F010A
device
s High performance
— 45 ns maximum access time
s Low power consumption
— 12 mA typical active read current
— 30 mA typical program/erase current
— <1 µA typical standby current
s Flexible sector architecture
— Eight 16 Kbyte sectors
— Any combination of sectors can be erased
— Supports full chip erase
s Sector protection
— Hardware-based feature that disables/re-
enables program and erase operations in any
combination of sectors
— Sector protection/unprotection can be
implemented using standard PROM
programming equipment
s Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases the chip or any
combination of designated sector
— Embedded Program algorithm automatically
programs and verifies data at specified address
s Erase Suspend/Resume
— Supports reading data from a sector not
being erased
s Minimum 1 million erase cycles guaranteed per
sector
s 20-year data retention at 125°C
— Reliable operation for the life of the system
s Package options
— 32-pin PLCC
— 32-pin TSOP
— 32-pin PDIP
s Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
s Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 22336 Rev: C Amendment/0
Issue Date: November 28, 2000
1 page  
CONNECTION DIAGRAMS
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8 PDIP
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
4 3 2 1 32 31 30
5 29
6 28
7 27
8 PLCC 26
9 25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
Am29F010B
5
5 Page 
Table 3. Am29F010B Autoselect Codes (High Voltage Method)
Description
A16 A13
A8
A5
to to to to
CE# OE# WE# A14 A10 A9 A7 A6 A2 A1
Manufacturer ID: AMD
Device ID: Am29F010B
L L H X X VID X L X L
L L H X X VID X L X L
Sector Protection Verification
L L H SA X VID X L X H
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
DQ7
to
A0 DQ0
L 01h
H 20h
01h
(protected)
L
00h
(unprotected)
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
quires a high voltage (VID) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 22337. Contact an
AMD representative to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by
spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Am29F010B
11
11 Page | ||
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| PDF Descargar | [ Datasheet AMD29F010B.PDF ] | |
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