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PDF MSM6882-5 Data sheet ( Hoja de datos )

Número de pieza MSM6882-5
Descripción (MSM6882-3/-5) 2400/1200 bps Single Chip MSK Modem
Fabricantes OKI electronic componets 
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No Preview Available ! MSM6882-5 Hoja de datos, Descripción, Manual

E2A0035-16-X0
¡¡SemicondSucetormiconductor
MSM6882-3/6882-5
2400/1200 bps Single Chip MSK Modem
ThisMveSrMsi6o8n8: 2J-a3n/.61898928-5
Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM6882-3/6882-5 is a single chip MSK (Minimum Shift Keying) modem which is fabricated
by Oki’s low power consumption CMOS silicon gate technology.
The demodulator receives the data to be transmitted (SD) synchronized with the transmit timing
clock (ST) generated by the on-chip clock generator. The signal, which is modulated by MSK method,
is output.
The demodulator converts the received MSK signal to the received data (RD) by means of a delay
detection technique after limiting the band of the received MSK signal. This signal is input to the
digital PLL and the re-generated timing clock (RT) is output from the demodulator, synchronized
with the RD.
FEATURES
• Signal power supply:+3.6 V (MSM6882-3)
+5 V (MSM6882-5)
• On-chip SCF (Switched Capacitor Filter)
• The transmit filter can be also used as voice splatter filter.
• The receive timing re-generator has two different lock-in time performance options to be chosen
from.
• Bit rate 2400/1200 bps
• CCIR Rec. 623
• The modulation method can be selected from COS-FFSK and SIN-FFSK.
• Built-in crystal oscillation circuit.
• Package options:
22-pin plastic DIP
(DIP22-P-400-2.54)
(Product name: MSM6882-3RS)
(Product name: MSM6882-5RS)
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM6882-3GS-K)
(Product name: MSM6882-5GS-K)
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MSM6882-5 pdf
¡ Semiconductor
MSM6882-3/6882-5
Name
BR
SG
GND
TI
Baud rate selection.
Master Clock
(MHz)
7.3728
3.6864
3.6864
MCS
1
1
0
1
1
Description
BR Bit Rate
(bps)
1 2400
0 1200
0 1200
1 1200
0 600
Carrier Freq. (Hz)
Mark
Space
1200
2400
1200
1800
1200
1800
600 1200
600 900
Built-in analog signal ground.
The DC voltage is approximately half of VDD, so the analog interfaces signals of AI, AO, and TI
with peripheral circuits which must be implemented by AC-coupling. To make this voltage
source impedance lower and ensure the device performance of this device, more than 0.1 mF
bypass capacitors should be connected from SG to GND and from SG to VDD.
Ground. (0 V)
Voice signal input.
The signal input to this pin can be sent out to AO through the transmit LPF, the characteristics
of which, gives the splatter filter for voice band signal.
When this function is used, digital "0" must be input to ME.
TI is biased to SG through internal resistor.
Transmit analog signal output.
The data put on ME and FT can set the status of AO as follows.
FT ME Transmit LPF
"1" "1"
"1" "0"
Power On
"0" "1"
Power Down
"0" "0"
State of AO
MSK Signal
Voice Signal
The Output of Receive BPF
No-signal (SG level)
TI Power down
AO
SD
Modu-
lator
Transmit LPF
SG
+
AO
Receive BPF
AI
The state when FT and ME = "0" is shown above. When the input digital data on FT changes to
"1" from "0", AO remains to be connected to SG during about 2 ms and after that, and AO is
switched to transmit LPF.
This delay time prevents AO from outputting meaningless signal during transient time from
power down to on of LPF.
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MSM6882-5 arduino
¡ Semiconductor
TIMING DIAGRAM
MSM6882-3/6882-5
ST
SD, PRE
50%
50%
tS tH
Figure 1 Input Data Timing
RT 50%
RD 50%
tD
Figure 2 Output Data Timing
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