PDF AM486DE2 Data sheet ( Hoja de datos )

Número de pieza	AM486DE2
Descripción	8K Write Through Embedded Microprocessor
Fabricantes	AMD
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FINAL Am486®DE2 8-Kbyte Write-Through Embedded Microprocessor DISTINCTIVE CHARACTERISTICS s High-Performance Design s Complete 32-Bit Architecture — 66-MHz operating frequency — Address and data buses — Frequent instructions execute in one clock — All registers — 105.6-million bytes/second burst bus at 33 MHz — 8-, 16-, and 32-bit data types — Flexible write-through address control s Standard Features — Dynamic bus sizing for 8-, 16-, and 32-bit buses — 3-V core with 5-V-tolerant I/O — Soft reset capability — Binary compatible with all Am486® DX s High On-Chip Integration and Am486DX2 microprocessors — 8-Kbyte unified code and data cache — Floating-point unit — Paged, virtual memory management s Enhanced System and Power Management — Wide range of support available through the AMD® FusionE86SM Program s IEEE 1149.1 JTAG Boundary-Scan Compatibility s Supports Environmental Protection Agency's Energy Star program — Stop clock control for reduced power consumption — 3-V operation reduces power consumption up to 40% — Industry-standard, two-pin System Management — Energy management capability provides an ex- Interrupt (SMI) for power management indepen- dent of processor operating mode and operating www.DataSheet4U.comsystem cellent base for energy-efficient design — Works with a variety of energy-efficient, power- managed devices — Static design with Auto Halt Power-Down support s 208-Lead SQFP or 168-Pin PGA Package — Wide range of chipsets supporting SMM avail- able to allow product differentiation GENERAL DESCRIPTION The Am486DE2 microprocessor is an addition to the AMD Am486 microprocessor family. The Am486DE2 enhances system performance by incorporating flexible clock control and enhanced SMM. The Am486DE2 CPU clock control feature permits the CPU to be stopped under controlled conditions, allowing reduced power consumption during system inactivity. The SMM function is implemented with an industry-stan- dard, two-pin interface. www.datasheet4u.com Publication ID Revision Amendment 20037 A /0 Issue Date April 1996 1 page WB/WT (New) ...................................................................................................................................... 16 W/R ...................................................................................................................................................... 16 Functional Description................................................................................................................................ 17 Overview .............................................................................................................................................. 17 Memory ................................................................................................................................................ 17 Modes of Operation ............................................................................................................................. 17 Write-Through Cache Architecture ...................................................................................................... 17 Cache Replacement Description ......................................................................................................... 17 Memory Configuration ......................................................................................................................... 17 Clock Control.............................................................................................................................................. 18 Clock Generation ................................................................................................................................. 18 Stop Clock ........................................................................................................................................... 18 Stop Grant Bus Cycle .......................................................................................................................... 19 Pin State During Stop Grant ................................................................................................................ 19 Clock Control State Diagram ............................................................................................................... 20 SRESET Function ...................................................................................................................................... 20 System Management Mode ....................................................................................................................... 22 Overview .............................................................................................................................................. 22 Terminology ......................................................................................................................................... 22 System Management Interrupt Processing.......................................................................................... 22 Entering System Management Mode .................................................................................................. 26 Exiting System Management Mode ..................................................................................................... 27 Processor Environment ....................................................................................................................... 27 Executing System Management Mode Handler .................................................................................. 28 SMM System Design Considerations .................................................................................................. 31 SMM Software Considerations ............................................................................................................ 34 Test Registers 4 and 5 Modifications ......................................................................................................... 36 TR4 Definition ...................................................................................................................................... 36 TR5 Definition ...................................................................................................................................... 36 Am486DE2 Microprocessor Functional Differences................................................................................... 37 Am486DE2 Microprocessor Identification .................................................................................................. 37 DX Register at RESET ........................................................................................................................ 37 CPUID Instruction ................................................................................................................................ 37 Electrical Data ............................................................................................................................................ 39 Power Connections.............................................................................................................................. 39 Power Decoupling Recommendations................................................................................................. 39 Other Connection Recommendations.................................................................................................. 39 Absolute Maximum Ratings........................................................................................................................ 40 Operating Ranges ...................................................................................................................................... 40 DC Characteristics over Commercial Operating Ranges ........................................................................... 40 Switching Characteristics over Commercial Operating Ranges................................................................. 41 Switching Characteristics for 33-MHz Bus (66-MHz Microprocessor) ................................................. 42 Switching Waveforms .......................................................................................................................... 43 Package Thermal Specifications ................................................................................................................ 48 Physical Dimensions .................................................................................................................................. 50 168-Pin PGA ........................................................................................................................................ 50 208-Lead SQFP ................................................................................................................................... 51 Am486DE2 Microprocessor 5 5 Page LOGIC SYMBOL Clock Stop Clock Address Mask Upgrade Present Voltage Detect Address Bus 28 2 4 Bus Cycle Control Bus Cycle Definition CLK STPCLK A20M UP VOLDET A31–A4 A3–A2 BE3–BE0 BS8 BS16 ADS RDY M/IO D/C W/R LOCK PLOCK Am486DE2 CPU Interrupts INTR NMI RESET SRESET HOLD BOFF BREQ HLDA IGNNE FERR D31–D0 32 Data Bus DP3–DP0 PCHK BRDY BLAST CACHE SMI SMIACT 4 PWT PCD WB/WT INV KEN FLUSH AHOLD EADS HITM Data Parity Burst Control SMM Page Cacheability Cache Control/ Invalidation TCK TDI TMS TDO Bus Arbitration Numeric Error Reporting IEEE Test Port Access Am486DE2 Microprocessor 11 11 Page

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