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PDF CY2DL814 Data sheet ( Hoja de datos )
| Número de pieza | CY2DL814 | |
| Descripción | 1:4 Clock Fanout Buffer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Features
• Low-voltage operation
• VDD = 3.3V
• 1:4 Fanout
• Single-input configurable for
— LVDS, LVPECL, or LVTTL
— Four differential pairs of LVDS outputs
• Drives 50- or 100-ohm load (selectable)
• Low input capacitance
• Low output skew
• Does not exceed Bellcore 802.3 standards
• Operation at ⇒ 350 MHz – 700 Mbps
• Low propagation delay Typical (tpd < 4 ns)
• Industrial versions available
• Packages available include TSSOP/SOIC
ComLink™ Series
CY2DL814
1:4 Clock Fanout Buffer
Description
The Cypress CY2 series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DL814 fanout buffer features a single
LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS
output pairs.
Designed for data-communication clock management applica-
tions, the fanout from a single input reduces loading on the
input clock.
The CY2DL814 is ideal for both level translations from single
ended to LVDS and/or for the distribution of LVDS-based clock
signals. The Cypress CY2DL814 has configurable input and
output functions. The input can be selectable for
LVPECL/LVTTL or LVDS signals while the output driver’s
support standard and high drive LVDS. Drive either a 50-ohm
or 100-ohm line with a single part number/device.
Block Diagram
EN1
EN2
IN+
IN-
LVDS /
LVPECL /
LVTTL
CONFIG
CNTRL
Pin Configuration
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
OUTPUT
LVDS
EN1
CONFIG
CNTRL
VDD
GND
IN+
IN-
EN2
1
2
3
4
5
6
7
8
16 Q1A
15 Q1B
14 Q2A
13 Q2B
12 Q3A
11 Q3B
10 Q4A
9 Q4B
16-pin TSSOP/SOIC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07057 Rev. *A
Revised December 14, 2002
1 page  
Table 12. High Frequency Parametrics
Parameter
Fmax
Fmax(20)
Description
Maximum frequency
VDD = 3.3V
Maximum frequency
VDD = 3.3 V
TW Minimum pulse
VDD = 3.3 V
Conditions
50% duty cycle tW(50–50)
Standard Load Circuit.
20% duty cycle tW(50–50)
LVPECL Input
VIN = VIH(Max.)/VIL(Min.)
VOUT = VOH(Min.)/VOL (Max.) (Limit)
LVPECL Input
VIN = VIH(Max.)/VIL(Min.) F= 100 MHz
VOUT = VOH(Min.)/VOL(Max.)(Limit)
Pulse
Generator
A
B
10pF
ComLink™ Series
CY2DL814
Min.
Typ.
Max.
400
Unit
MHz
200 MHz
1 ns
TPA
50
TPC
50
TPB
Standard Termination
V1A
1.2 V CM
V1B
V0Y
1.2 V CM
V0Z
TPLH
TPHL
V0Y - V0Z
1.4 V
0V Differential
1.0 V
1.4 V
0V Differential
1.0 V
80%
0V Differential
20%
tR tF
Figure 1. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3,4,5,6]
Pulse
Generator
A
B
TPA
50
TPC
50
TPB
Standard Termination
VOC
VOD
Next Device
VI(A)
2.0V
VI(B)
1.6V
Figure 2. Test Circuit and Voltage Definitions for the Driver Common-mode Output Voltage[3,4,5,6]
Notes:
3. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF ≤ 1 ns; pulse rerate = 50 Mpps; pulse width = 10 ± 0.2 ns.
4. RL= 50 ohm ± 1% Zline = 50 ohm 6”.
5. CL includes instrumentation and fixture capacitance within 6 mm of the UT.
6. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to VDD- 2.
Document #: 38-07057 Rev. *A
Page 5 of 8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CY2DL814.PDF ] | |
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