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PDF L64118 Data sheet ( Hoja de datos )
| Número de pieza | L64118 | |
| Descripción | MPEG-2 Transport Controller | |
| Fabricantes | LSI Logic | |
| Logotipo |  |
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L64118 MPEG-2 Transport
Controller with
Embedded MIPS CPU (TR4101)
Preliminary Datasheet
®
LSI Logic’s L64118 MPEG-2 Transport Controller with Embedded MIPS
CPU (TR4101) is a highly integrated set-top box control and
communication device, combining most of the logic needed for a digital
broadcast system (DBS) or cable set-top box onto a single chip. The
L64118’s embedded 32-bit TinyRISC™ MIPS CPU core provides
processing power to support transport and system data, as well as
general-purpose system control.
The L64118 interfaces directly to LSI Logic’s L64704 and L64724
(satellite), and the L64768 (cable) single-chip channel decoders, as well
as to the L64105 MPEG-2 A/V decoder.
The MPEG-2 transport and system demultiplexer can handle 32 Packet
Identifications (PIDs) simultaneously, including audio, video, and general-
purpose data services. It integrates a Digital Video Broadcasting (DVB)-
compliant descrambler block, substantially increasing the security of the
set-top box.
The L64118’s synchronous External System Bus (EBus) communicates
with external peripherals. The L64118 communicates with peripherals
through serial, parallel, SmartCard, and infrared ports. Several general-
purpose I/O pins are provided that let system designers expand the
system’s capabilities.
The L64118 supports industry-standard SDRAM memory of up to
16 Mbytes, using 16 and 64 Mbit SDRAMs. The SDRAM interface
supports PC66/100-compliant SDRAMS.
mThe L64118 is offered in LSI Logic’s 3.3 V G10®-p cell-based technology
oand is packaged in a 256-pin PBGA (IF) package.
w.datasheet4u.cFebruary 1999
ww Copyright © 1997, 1998 by LSI Logic Corporation. All rights reserved.
1
1 page  
• Two 256-byte transport buffers for supporting audio and video PES
streams
• 32 programmable cyclic buffers in SDRAM memory assignable to a
PID or section filter index
• Support for an additional programmable cyclic buffer in SDRAM to
post data to adaptation fields
• Program Clock Reference (PCR) recovery and locking
• Automatic detecting and switching of audio and video PIDs on splice
points
• Audio oversampling (256 or 384 times oversampling) clock
generation
CPU and Subsystems
• Integration of the CPU system:
– 32-bit TR4101 54 MHz TinyRISC CPU
– MIPS16 and MIPS-II instruction set compatible
– Four Kbyte Data (direct mapped) and Eight Kbyte (two-way set
associative) instruction cache
– Basic Bus and Cache Controller unit (BBCC)
– Multiply/Divide Unit (MDU)
– Debugger Building Module (DBX)
– 32-bit Timers and Interrupt Controller
– In-Circuit Emulator (ICE) port
• Two interrupt handling modes:
– Interrupt Compatibility mode supports 12 interrupt ports and six
main interrupt levels. This mode is compatible with the L64108
interrupt structure.
– Interrupt Extension mode supports 25 interrupt ports with a
software index to each interrupt source. This new mode can
reduce interrupt latency.
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 5
5 Page 
SDRAM controller module. The block includes a PID processor unit
(PPU) that is compliant with DVB and JSAT and meets the requirements
of many other service providers, including Canal+, SkyPerfect, and
BSkyB.
The unit can process up to 32 PIDs simultaneously. It provides extensive
filtering of PSI, SI, and Private Sections. The PSI, SI, and Private
Sections are filtered according to 32 user-programmable match/mask
PIDs. Section data that passes filtering is stored in cyclic buffers (in off-
chip memory) associated with each PID. Each section in each PID can
be filtered against 32 filters. (Every section undergoes a CRC32 check.
An enable bit controls the CRC checking of all section types.) The on-
chip descrambler unit increases system security. The audio and video
data are reduced to PES streams and delivered to the A/V decoder.
SDRAM Controller
The SDRAM controller and resource arbitration logic makes efficient use
of SDRAM bandwidth. This chip’s low-cost system implementation
approach dictates usage of the external SDRAM for both transport and
general system functions. The L64118 supports various SDRAM
configurations using 16 Mbit and 64 Mbit devices, for a total memory size
of 2, 8, or 16 Mbytes of external SDRAM.
The SDRAM controller arbitrates access to the external SDRAM. This
logic provides the maximum possible SDRAM bandwidth to the on-chip
CPU without increasing the need for buffers or other resources.
External System Bus (EBus)
The External System Bus is a general-purpose 16- and 32-bit system
bus used for communication with external components in the system.
This bus provides the system designer with an interface that permits the
glueless connection of devices like FLASH, ROMs, and external
peripherals.
The EBus comprises a 32-bit wide interface with multiplexed address and
data. Eight address bits are available as demultiplexed bits for easy
interface to devices that do not need the full address space. In addition
a demultiplexed mode can be configured to provide a 24-bit address and
16-bit data bus.
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet L64118.PDF ] | |
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