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PDF ICS950410 Data sheet ( Hoja de datos )
| Número de pieza | ICS950410 | |
| Descripción | AMD - K System Clock Chip | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS950410 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS950410
Advance Information
AMD - K8™ System Clock Chip
Recommended Application:
AMD K8 System Clock with AMD, VIA or ALI Chipset
Pin Configuration
~*FS0/REF0 1
48 REF1/FS1*
Output Features:
VDDHTT 2
• 3 - Differential pair push-pull CPU clocks @
X1 3
3.3V
X2 4
• 9 - PCICLK (Including 1 free running) @ 3.3V
GND 5
• 3 - Selectable PCICLK/HTTCLK @ 3.3V
*ModeA/HTTCLK0 6
• 1 - HTTCLK @ 3.3V
*ModeB/PCICLK8/HTTCLK1 7
• 1 - 48MHz @ 3.3V fixed.
PCICLK9/HTTCLK2 8
• 1 - 24/48MHz @ 3.3V
VDDPCI 9
• 2 - REF @ 3.3V, 14.318MHz.
GND 10
Features:
PCICLK11/HTTCLK3 11
• Programmable output frequency.
*FS2/PCICLK10 12
• Programmable output divider ratios.
PCICLK0 13
• Programmable output rise/fall time.
PCICLK1 14
• Programmable output skew.
GND 15
• Programmable spread percentage for EMI
control.
• Watchdog timer technology and RESET# output
to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/
write operations.
VDDPCI 16
PCICLK2 17
PCICLK3 18
VDDPCI 19
GND 20
2XPCICLK4 21
2XPCICLK5 22
• Uses external 14.318MHz crystal.
2XPCICLK6 23
• Supports Hyper Transport Technology (HTTCLK).
2XPCICLK7 24
47 GND
46 VDDREF
45 Reset#
44 VDDA
43 GND
42 CPUCLK8T0
41 CPUCLK8C0
40 VDDCPU
39 CPUCLK8T1
38 CPUCLK8C1
37 GND
36 VDDCPU
35 CPUCLK8T2
34 CPUCLK8C2
33 GND
32 Turbo#
31 PD#*
30 48MHz/FS3**
29 GND
28 AVDD48
27 24_48MHz/Sel24_48#*
26 SDATA
25 SCLK
48-SSOP
Functionality
FS3 FS2 FS1 FS0 CPU
MHz
HTT
MHz
0 0 0 0 100.90 67.27
0 0 0 1 133.90 66.95
0 0 1 0 168.00 67.20
0 0 1 1 202.00 67.33
0 1 0 0 100.20 66.80
0 1 0 1 133.50 66.75
0 1 1 0 166.70 66.68
0 1 1 1 200.40 66.80
1 0 0 0 150.00 60.00
PCI
MHz
33.63
33.48
33.60
33.67
33.40
33.38
33.34
33.40
30.00
* Internal Pull-Up Resistor
2X This Output has 2X Default Drive and can be programmaed lower via IIC
~ This Output has 1.5x drive
1 0 0 1 180.00 60.00 30.00
1 0 1 0 210.00 70.00 35.00
1 0 1 1 240.00 60.00 30.00
1 1 0 0 270.00 67.50 33.75
1 1 0 1 233.33 66.67 33.33
1 1 1 0 266.67 66.67 33.33
1 1 1 1 300.00 75.00 37.50
0888—04/06/04
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
1 page  
ICS950410
Advance Information
General I2C serial interface information
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
T starT bit
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P stoP bit
ACK
0888—04/06/04
5
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
T starT bit
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address D3(H)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N Not acknowledge
P stoP bit
Byte N + X - 1
5 Page 
ICS950410
Advance Information
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
SYMBOL
CONDITIONS*
MIN TYP MAX
Output Impedance
RDSP
VO = VDD*(0.5)
12
Output High Voltage
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
IOL = 1 mA
Output High Current
IOH
V OH @MIN = 1.0 V
VOH@MAX = 3.135 V
-33
Output Low Current
IOL
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
30
Edge Rate
tslewr/f
Rising/Falling edge rate
1
Rise Time
tr
VOL = 0.4 V, VOH = 2.4 V
0.5
Fall Time
tf
VOH = 2.4 V, VOL = 0.4 V
0.5
Duty Cycle
dt1
VT = 1.5 V
45
Group Skew
tskew
VT = 1.5 V
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω (unless otherwise specified)
1Guaranteed by design and characterization, not 100% tested in production.
55
0.55
-33
38
4
2
2
55
250
500
3 Spread Spectrum is off
UNITS
Ω
V
V
mA
mA
mA
mA
V/ns
ns
ns
%
ps
ps
NOTES
1
1
1
1
1
1
1
1
1
1
1
1
1
Electrical Characteristics - 48MHz/USB48MHz/24_48MHz
PARAMETER
Long Accuracy
SYMBOL
CONDITIONS*
ppm see Tperiod min-max values
MIN
-100
TYP
MAX
100
Clock period
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Edge Rate
Tperiod
RDSP
VOH
VOL
IOH
IOL
tslewr/f
48.00MHz output nominal
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising/Falling edge rate
20.8313
12
2.4
-33
30
1
20.8354
55
0.55
-33
38
4
Edge Rate
tslewr/f_USB USB48 Rising/Falling edge rate
1
2
Rise Time
tr
VOL = 0.4 V, VOH = 2.4 V
0.5
2
Fall Time
tf
VOH = 2.4 V, VOL = 0.4 V
0.5
2
Rise Time
tr_USB
VOL = 0.4 V, VOH = 2.4 V
1
2
Fall Time
tf_USB
VOH = 2.4 V, VOL = 0.4 V
1
2
Duty Cycle
dt1
VT = 1.5 V
45
55
Group Skew
tskew
VT = 1.5 V
250
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
500
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω (Rs is used in USB48MHz test only)
1Guaranteed by design and characterization, not 100% tested in production.
UNITS
ppm
ns
Ω
V
V
mA
mA
mA
mA
V/ns
V/ns
ns
ns
ns
ns
%
ps
ps
NOTES
1,2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0888—04/06/04
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ICS950410.PDF ] | |
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