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PDF ICS950227 Data sheet ( Hoja de datos )
| Número de pieza | ICS950227 | |
| Descripción | Programmable Timing Control Hub for P4 | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS950227 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS950227
Programmable Timing Control Hub™ for P4™
Recommended Application:
CK-408 clock Intel® 845 with P4 processor.
Output Features:
• 3 Differential CPU Clock Pairs @ 3.3V
• 7 PCI (3.3V) @ 33.3MHz
• 3 PCI_F (3.3V) @ 33.3MHz
• 1 USB (3.3V) @ 48MHz
• 1 DOT (3.3V) @ 48MHz
• 1 REF (3.3V) @ 14.318MHz
• 5 3V66 (3.3V) @ 66.6MHz
• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features/Benefits:
• Programmable output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz crystal.
Key Specifications:
• CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps
Pin Configuration
VDDREF 1
X1 2
X2 3
GND 4
PCICLK_F0 5
PCICLK_F1 6
PCICLK_F2 7
VDDPCI 8
GND 9
PCICLK0 10
PCICLK1 11
PCICLK2 12
PCICLK3 13
VDDPCI 14
GND 15
PCICLK4 16
PCICLK5 17
PCICLK6 18
VDD3V66 19
GND 20
3V66_2 21
3V66_3 22
3V66_4 23
3V66_5 24
*PD# 25
VDDA 26
GND 27
Vtt_PWRGD# 28
56 REF
55 FS1
54 FS0
53 CPU_STOP#*
52 CPUCLKT0
51 CPUCLKC0
50 VDDCPU
49 CPUCLKT1
48 CPUCLKC1
47 GND
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
43 MULTSEL0*
42 IREF
41 GND
40 FS2
39 48MHz_USB
38 48MHz_DOT
37 VDD48
36 GND
35 3V66_1/VCH_CLK
34 PCI_STOP#*
33 3V66_0
32 VDD3V66
31 GND
30 SCLK
29 SDATA
56-Pin 300-mil SSOP
* These inputs have 150K internal pull-up resistor to VDD.
Block Diagram
PLL2
X1 XTAL
OSC
WDEN
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (2:0)
SDATA
SCLK
Vtt_PWRGD#
PLL1
Spread
Spectrum
Control
Logic
Config.
Reg.
0641D—07/03/03
CPU
DIVDER
Stop
PCI
DIVDER
Stop
3V66
DIVDER
Frequency Table
48MHz_USB
48MHz_DOT
3V66_1/VCH_CLK
REF
3 CPUCLKT (2:0)
3 CPUCLKC (2:0)
PCICLK (6:0)
7
PCICLK_F (2:0)
3
3V66 (5:2,0)
5
FS2 FS1 FS0
CPU
(MHz)
3V66
(MHz)
66Buff[2:0]
3V66[4:2]
(MHz)
PCI_F
PCI
(MHz)
0 0 0 66.66 66.66
66.66
33.33
0 0 1 100.00 66.66
66.66
33.33
0 1 0 200.00 66.66
66.66
33.33
0 1 1 133.33 66.66
66.66
33.33
Mid 0 0 Tristate Tristate Tristate Tristate
Mid 0 1 TCLK/2 TCLK/4 TCLK/4 TCLK/8
Mid 1 0 Reserved Reserved Reserved Reserved
Mid 1 1 Reserved Reserved Reserved Reserved
I REF
1 page  
Integrated
Circuit
Systems, Inc.
ICS950227
I2C Table: Frequency Select Register
Byte 0
Bit 7
Pin #
-
Name
SPREAD ENABLE
Control Function
Frequency H/W IIC
Select
Bit 6
- CENTER/DOWNSP CENTER/DOWNSPRE
READ SELECT
AD SELECT
Bit 5
35 3V66/VCH SELECT 48MHz/66.66MHz SEL
Bit 4
53
CPU_STOP# CPU STOP Read Back
Bit 3
Bit 2
Bit 1
Bit 0
34
PCI_STOP#
HW/SW SELECT
Freq Select Bit 3
40
FS2
Freq Select 2 Read
Back
55
FS1
Freq Select 1 Read
Back
54
FS0
Freq Select 0 Read
Back
Type
RW
RW
RW
R
RW/R
R
R
R
0
OFF
1
ON
DOWN
SPREAD
66.66MHz
CENTER
SPREAD
48.00MHz
READBACK
PCI STOP
PCI
RUNNING
READBACK
PWD
0
0
0
X
1
X
X
X
I2C Table: Spreading and Device Behavior Control Register
Byte 1
Bit 7
Bit 6
Pin #
43
-
Name
MULTSEL0
WD ALARM
Control Function
MULTSEL0
READBACK
Watchdog Alarm Read
Back
Bit 5
45, 44
CPU2/CPUC2
Bit 4
49, 48
CPU FREE-RUN NING
CPU1/CPUC1
CONTROL
Bit 3
52, 51
CPU0/CPUC0
Bit 2
Bit 1
Bit 0
45, 44
49, 48
52, 51
CPU2/CPUC2
CPU1/CPUC1
CPU0/CPUC0
Output Control
Output Control
Output Control
Type
R
R
RW
RW
RW
RW
RW
RW
01
READBACK
NO ALARM ALARM SET
STOPPABLE FREE-RUN
STOPPABLE FREE-RUN
STOPPABLE FREE-RUN
Disable
Disable
Disable
Enable
Enable
Enable
PWD
X
0
0
0
0
1
1
1
I2C Table: Output Control Register
Byte 2
Pin #
Name
Bit 7
-
Reserved
Bit 6
Bit 5
18
17
PCICLK6
PCICLK5
Bit 4
16
PCICLK4
Bit 3
Bit 2
13
12
PCICLK3
PCICLK2
Bit 1
11
PCICLK1
Bit 0
10
PCICLK0
Control Function
Reserved
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
-
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
0
1
1
1
1
1
1
1
I2C Table: Output Control Register
Byte 3
Bit 7
Bit 6
Pin #
38
39
Name
48MHz_DOT
48MHz_USB
Bit 5
7
PCIF2
Bit 4
6
PCIF1
Bit 3
Bit 2
Bit 1
Bit 0
0641D—07/03/03
5
7
6
5
PCIF0
PCICLK_F2
PCICLK_F1
PCICLK_F0
Control Function
Output Control
Output Control
CPU FREE-RUN NING
CONTROL
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
1
Enable
Enable
FREE-RUN STOPPABLE
FREE-RUN STOPPABLE
FREE-RUN STOPPABLE
Disable
Disable
Disable
Enable
Enable
Enable
PWD
1
1
0
0
0
1
1
1
5
5 Page 
Integrated
Circuit
Systems, Inc.
ICS950227
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
MAX
Input High Voltage
VIH
2 VDD + 0.3
Input Low Voltage
Input High Current
Input Low Current
VIL VSS - 0.3
IIH
VIN = VDD
-5
IIL1
VIN = 0 V; Inputs with no pull-up
resistors
-5
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
0.8
5
UNITS
V
V
mA
mA
Operating Supply Current
IDD3.3OP
CL = Full load
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance1
Clk Stabilization1,2
IDD3.3PD
Fi
Lpin
CIN
COUT
CINX
TSTAB
IREF=2.32 mA
VDD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From PowerUp or deassertion of
PowerDown to 1st clock.
Delay1
tPZH,tPZL Output enable delay (all outputs)
tPHZ,tPLZ Output disable delay (all outputs)
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for buffered and un-buffered timing requirements.
27
1
1
283
23
14.32
360
25
7
5
6
45
1.8
10
10
mA
mA
MHz
nH
pF
pF
pF
ms
ns
ns
0641D—07/03/03
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ICS950227.PDF ] | |
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