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PDF MBM30LV0064 Data sheet ( Hoja de datos )
| Número de pieza | MBM30LV0064 | |
| Descripción | 64M (8M X 8) BIT NAND-type | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20878-3E
FLASH MEMORY
CMOS
64M (8M × 8) BIT NAND-type
MBM30LV0064
s DESCRIPTION
The MBM30LV0064 device is a single 3.3 V 8M × 8 bit NAND flash memory organized as 528 byte × 16 pages
× 1024 blocks. Each 528 byte page contains 16 bytes of optionally selected spare area which may be used to
store ECC code(Specifications indecated are on condition that ECC system would be combined.). Program and
read data is transferred between the memory array and page register in 528 byte increments. A 528 byte page
can be programmed in 200 µs and an 8K byte block can be erased in 2 ms under typical conditions. An internal
controller automates all program and erase operations including the verification of data margins. Data within a
page can be read with a 50 ns cycle time per byte. The I/O pins are utilized for both address and data input/
output as well as command inputs. The MBM30LV0064 is an ideal solution for applications requiring mass non-
volatile storage such as solid state file storage, digital recording, image file memory for still cameras, and other
uses which require high density and non-volatile storage.
s PRODUCT LINE UP
Part No.
Operating Temperature
VCC
Read
Power Dissipation (Max.)
Erase / Program
TTL Standby
CMOS Standby
s PACKAGES
44-pin plastic TSOP (II)
Marking Side
MBM30LV0064
–40°C to +85°C
+2.7 V to +3.6 V
72 mW
72 mW
3.6 mW
0.18 mW
(FPT-44P-M07)
(Normal Bend)
Marking Side
(FPT-44P-M08)
(Reverse Bend)
1 page  
s BLOCK DIAGRAM
ALE
CLE
SE
WP
CE
RE
WE
VCC
VCCq
VSS
High Voltage Pumps
State Machine
Command Register
Address Register
Status Register
MBM30LV0064
Y-Decoder
Data Register & S/A
Memory Array
Data Register & S/A
Y-Decoder
R/B
I/O Register & Buffer
I/O0 to I/O7
5
5 Page 
MBM30LV0064
Page Program: 80h, 10h
The device is programmed either by the page or partial page. Programming is done by issuing the 80h command
followed by three address cycles then serial data input. The 80h command may be preceded by either 00h, 01h
or 50h to set the pointer to either the first half page, second half page, or spare area respectively. If the pointer
command is not specifically issued, its location is determined by its previous use (see Application Note (2) ).
After the serial data input, any column address which did not receive new data will not be programmed. This
enables a page to be partially programmed. After the data has been entered, the 10h command will initiate the
embedded programming process. If the 10h command is issued without loading any new data, programming
will not be initiated. A given page may not be partially programmed more than ten consecutive times without an
intervening erase operation. During the programming cycle, the R/B pin or Status Register bit I/O6 may be used
to monitor the completion of the programming cycle. Only the Reset and Read Status commands are valid while
programming is in progress. After programming, the Status Register bit I/O0 should be checked to verify whether
the procedure was successful or not.
R/B
I/O0 to I/O7
80h Address and Data Input 10h
Figure 5 Page Program
70h I/O0
0 = Pass
1 = Fail
Block Erase: 60h
The device data is erased in a block consisting of sixteen pages. The erase operation begins with the 60h
command followed by two address cycles in which the block to be erased is entered. While the two address
cycles require A22 to A9 to be entered, A12 to A9 are don’t care bits. Once the block address is successfully loaded,
the D0h command is entered to initiate the erase operation. The R/B signal may be used to monitor the completion
of the cycle. Upon completion, the Status Register bit I/O0 should be used to verify a successful erase.
R/B
I/O0 to I/O7
60h
Address Input
D0h
Figure 6 Block Erase
70h I/O0
0 = Pass
1 = Fail
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MBM30LV0064.PDF ] | |
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