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PDF DSPA56371 Data sheet ( Hoja de datos )
| Número de pieza | DSPA56371 | |
| Descripción | 24-BIT CMOS | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Freescale Semiconductor
Technical Data
DSP56371
Rev. 3, 1/2005
1 Introduction
The DSP56371 is a high density CMOS device with 5.0-volt compatible inputs and outputs.
NOTE
This document contains information on a new product.
Specifications and information herein are subject to
change without notice.
Finalized specifications may be published after further characterization and device
qualifications are completed.
2 DSP56371 Overview
2.1 Introduction
This manual describes the DSP56371 24-bit digital signal processor (DSP), its memory,
operating modes and peripheral modules. The DSP56371 is a member of the DSP56300
family of programmable CMOS DSPs. The DSP56371 is targeted to applications that
require digital audio compression/decompression, sound field processing, acoustic
equalization and other digital audio algorithms. Changes in core functionality specific to the
DSP56371 are also described in this manual. See Figure 1. for the block diagram of the
DSP56371.
Table of Contents
Section
Page
1 Introduction ................................... 1
2 DSP56371 Overview..................... 1
3 Signal/Connection Descriptions .... 8
4 Maximum Ratings ....................... 30
5 Power Requirements................... 32
6 Thermal Characteristics.............. 32
7 DC Electrical Characteristics ...... 33
8 AC Electrical Characteristics....... 34
9 Internal Clocks ............................ 34
10 External Clock Operation .......... 35
11 Reset, Stop, Mode Select, and
Interrupt Timing ........................... 36
12 Serial Host Interface SPI Protocol
Timing.......................................... 39
13 Serial Host Interface (SHI) I2C
Protocol Timing ........................... 44
14 Enhanced Serial Audio Interface
Timing.......................................... 46
15 Digital Audio Transmitter Timing51
16 Timer Timing ............................. 51
17 GPIO Timing ............................. 52
18 JTAG Timing ............................. 53
19 Package Information ................. 55
20 Design Considerations.............. 61
21 Power Consumption Benchmark63
22 IBIS Model ................................ 66
This document contains certain information on a new pr oduct.
Specifications and information herein ar e subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
DSP56371 Technical Data
1 page  
DSP56371 Overview
2.4.2 Address Generation Unit (AGU)
The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory
and contains the registers used to generate the addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-
around modulo and reverse-carry. The AGU operates in parallel with other chip resources to minimize address-generation
overhead.
The AGU is divided into two halves, each with its own Address ALU. Each Address ALU has four sets of register triplets, and
each register triplet is composed of an address register, an offset register and a modifier register. The two Address ALUs are
identical. Each contains a 24-bit full adder (called an offset adder).
A second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo value that is stored in its
respective modifier register. A third full adder (called a reverse-carry adder) is also provided.
The offset adder and the reverse-carry adder are in parallel and share common inputs. The only difference between them is that
the carry propagates in opposite directions. Test logic determines which of the three summed results of the full adders is output.
Each Address ALU can update one address register from its respective address register file during one instruction cycle. The
contents of the associated modifier register specifies the type of arithmetic to be used in the address register update calculation.
The modifier value is decoded in the Address ALU.
2.4.3 Program Control Unit (PCU)
The PCU performs instruction prefetch, instruction decoding, hardware DO loop control and exception processing. The PCU
implements a seven-stage pipeline and controls the different processing states of the DSP56300 core. The PCU consists of the
following three hardware blocks:
• Program decode controller (PDC)
• Program address generator (PAG)
• Program interrupt controller
The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control.
The PAG contains all the hardware needed for program address generation, system stack and loop control. The Program
interrupt controller arbitrates among all interrupt requests (internal interrupts, as well as the five external requests: IRQA, IRQB,
IRQC, IRQD and NMI) and generates the appropriate interrupt vector address.
PCU features include the following:
• Position independent code support
• Addressing modes optimized for DSP applications (including immediate offsets)
• On-chip instruction cache controller
• On-chip memory-expandable hardware stack
• Nested hardware DO loops
• Fast auto-return interrupts
The PCU implements its functions using the following registers:
• PC—program counter register
• SR—Status register
• LA—loop address register
• LC—loop counter register
• VBA—vector base address register
• SZ—stack size register
• SP—stack pointer
• OMR—operating mode register
• SC—stack counter register
The PCU also includes a hardware system stack (SS).
Freescale Semiconductor
DSP56371 Technical Data
5
5 Page 
3.2 Power
Signal/Connection Descriptions
Table 2. Power Inputs
Power Name
Description
PLLA_VDD (1) PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with
PLLP_VDD(1) an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate
external decoupling capacitors.
PLLD_VDD (1) PLL Power— The voltage (1.25 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate
external decoupling capacitors.
CORE_VDD (4) Core Power—The voltage (1.25 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate
decoupling capacitors.
IO_VDD (5)
SHI, ESAI, ESAI_1, DAX and Timer I/O Power —The voltage (3.3 V) should be well-regulated
and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail.
This is an isolated power for the SHI, ESAI, ESAI_1, DAX and Timer I/O. The user must provide
adequate external decoupling capacitors.
SDO5_SDI0_PC7
IO_GND
IO_VDD
SDO3_SDI2_PC8
SDO2_SDI3_PC9
SDO1_PC10
SDO0_PC11
CORE_VDD
PF8
PF6
PF7
CORE_GND
PF2
PF3
PF4
PF5
IO_VDD
PF1
PF0
IO_GND
ESAI
1
2
3
4
5
6
7
8
9
10
11
12
13 GPIO
14
15
16
17
18
19
20
Timer
DAX
ESAI_1
OnCE
Int/Mod
PLL
SHI
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
FST_PE4
SDO5_SDI0_PE6
SDO4_SDI1_PE7
SDO3_SDI2_PE8
SDO2_SDI3_PE9
SDO1_PE10
SDO0_PE11
CORE_GND
CORE_VDD
MODB_IRQA
MODB_IRQB
MODC_IRQC
MODD_IRQD
RESET_B
PINIT_NMI
EXTAL
PLLD_VDD
PLLD_GND
PLLP_GND
PLLP_VDD
3.3V
Figure 3. VDD Connections
1.25V
Freescale Semiconductor
DSP56371 Technical Data
11
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