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PDF AM79213 Data sheet ( Hoja de datos )
| Número de pieza | AM79213 | |
| Descripción | (AM79C203/031 / AM79213) PCM CODEC | |
| Fabricantes | Legerity | |
| Logotipo |  |
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Am79213/Am79C203/031
Advanced Subscriber Line Interface Circuit (ASLIC™) Device
Advanced Subscriber Line Audio-Processing Circuit
(ASLAC™) Device
DISTINCTIVE CHARACTERISTICS
Performs all of the functions of a codec-filter
Single channel architecture
Performs Battery-feed, Ring-trip, Signaling,
Coding, Hybrid and Test (BORSCHT) functions
Single hardware design meets multiple country
requirements through software programming
Standard microprocessor interface
Industry standard PCM interface with full-time
slot assignment
Monitor of two-wire interface voltage and current
for subscriber line diagnostics
Low idle power per line
On-hook transmission
Only battery and +5 V supplies needed
Exceeds LSSGR and CCITT central office
requirements
Off-hook and ground-key detectors with
programmable thresholds
Programmable line feed characteristics
independent of battery voltage
Built-in voice path test modes
Analog and digital hybrid balance capability
Adaptive hybrid balance capability
Linear power feed with power management and
thermal shutdown features
Abrupt and smooth polarity reversal
Power-cross detection in Ringing and Non-
ringing states
Software programmable
— DC loop feed characteristics and current limit
— Loop supervision detection thresholds
— Off-hook detect debounce interval
— Two-wire AC impedance
— Transhybrid balance
— Transmit and receive gains
— Equalization
— Digital I/O pins
— A-law/µ-law selection
Linear data available on PCM ports for custom
compression and expansion
Compatible with inexpensive protection
networks. Accommodates low tolerance fuse
resistors while maintaining longitudinal balance
to Bellcore specifications.
Power/Service Denial state
Small physical size
Integrated ring trip function
Four relay drivers with built-in energy
absorption zener diodes
Synchronized ring relay operation: zero volts ac
on, zero current off
Software enabled Normal or Automatic Ring-Trip
state
On-chip 12 kHz and 16 kHz metering generation
with on and off meter pulse shaping
Supports loop-start and ground-start signaling
0°C to +70°C commercial operation guaranteed
by production testing
–40°C to +85°C temperature range operation
available
Publication# 080160 Rev: D Amendment: /0
Issue Date: April 2000
1 page  
ORDERING INFORMATION
ASLIC Device
Must order Am79C203 or Am79C2031 with the device below.
Am79213
JC
TEMPERATURE RANGE
C = Commercial (0°C to 70°C)*
PACKAGE TYPE
J = 32-pin Plastic Leaded Chip Carrier (PL 032)
DEVICE NUMBER/DESCRIPTION
Am79213
Advanced Subscriber Line Interface Circuit
Valid Combinations
Am79213
JC
Valid Combinations
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local Legerity sales office to confirm availabil-
ity of specific valid combinations and to check on
newly released combinations.
Note:
* Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C
is guaranteed by characterization and periodic sampling of production units.
ASLIC/ASLAC Products
5
5 Page 
Pin Names
IDC
IDIF
INT
I/O1, I/O2, I/O3,
I/O4
IREF
IRTA, IRTB
ISUM
MCLK
PCLK
RST
TSCA, TSCB
VCCA
VCCD
VIN
Type
Output
Input
Output, Active
Low
Input/output
Reference
Inputs
Input
Input
Input
Input, Active
Low
Open Drain
Outputs
Power
Power
Input
Description
DC Loop Control Current. The IDC output supplies a current to the ASLIC device for pro-
portional control of the DC loop current flowing through the subscriber loop.
Longitudinal Sense. IDIF is a current input pin fed by the IDIF pin of the ASLIC device.
The current in this pin is used by the ASLAC device for supervisory and diagnostic func-
tions. The IDIF pin has an internal input resistance so an external longitudinal noise filter
capacitor can be connected.
Interrupt. A logic 0 on this pin indicates one or more of the bits in the signaling register
has changed states. An interrupt will be generated when activity is sensed on any signal
in the Signaling Register not masked by the Mask Register. Once an unmasked activity
is sensed, the INT output will be driven Low and held at that state until cleared. See the
description of configuration register 6 for operation.
Control Ports. These control lines are TTL compatible and each can be programmed as
an input or an output. When programmed as inputs, they can monitor external, TTL com-
patible logic circuits. When programmed as outputs, they can control an external logic de-
vice or they can be connected to pin C3, C4, or C5 of the ASLIC device to control test
relay drivers RY1OUT, RY2OUT and RY3OUT (I/O3, I/O4, 44-pin PLCC version only). In
the Output mode, these pins are controlled by the I/O1, I/O2, I/O3, and I/O4 bits in the
Channel Control Register, MPI Command 17.
Current Reference. An external resistor (RREF) connected between this pin and analog
ground generates an accurate on-chip reference current. This current is used by the
ASLAC device in its DC Feed and loop-supervision circuits.
Ring Trip Sense. These pins are current summing nodes referenced to VREF. They pro-
vide terminations for external resistors RSR1 and RSR2, which sense the voltages on
both sides of the ringing feed resistor connected to the ring bus. To determine the ring-
ing current in the loop, the ASLAC device senses the difference between the currents
in these pins.
Metallic Sense. ISUM is a current input pin and is fed by the ISUM pin of the ASLIC de-
vice. The absolute value of the current in this pin is used by the ASLAC device for super-
visory and diagnostic functions.
Master Clock. The master clock is used to operate the digital signal processor. MCLK
can be 2.048 MHz, 4.096 MHz or 8.192 MHz. MCLK may be asynchronous to PCLK.
Upon initialization, the MCLK input is disabled and relevant circuitry is driven by a
connection to PCLK. The MCLK connection may be reestablished under user control.
PCM Clock. The PCM clock determines the rate at which PCM data is serially shifted into
or out of the PCM ports. PCLK is an integer multiple of the frame sync frequency. The
maximum clock frequency is 8.192 MHz and the minimum clock frequency is 128 kHz for
companded data. The minimum clock frequency for linear or companded data plus sig-
naling data is 256 kHz. The PCLK clock may be asynchronous to MCLK if the initial con-
nection state is disabled under user control.
Reset. A logic 0 on this pin resets the ASLAC device to initial default conditions. It is
equivalent to a hardware reset command. A signal less than 100 ns should not cause
a reset. To ensure proper reset, the minimum length of a reset pulse is 50 µs.
Time Slot Control. The time slot control outputs are open drain (requiring an external
pull-up resistor to VCCD) and are normally inactive (high impedance). TSCA is active
(Low) when PCM data is present on DXA, and TSCB is active (Low) when PCM data is
present on DXB. (TSCB and DRB – 44-pin PLCC only.)
Analog Power Supply. VCCA is internally connected to substrate near the analog I/O
section.
Digital Power Supply. VCCD is internally connected to substrate near the digital section.
Analog Input. The analog output (VTX) from the ASLIC device is applied to the ASLAC
device transmit path input, VIN. The signal is sampled, processed, encoded, and trans-
mitted on the PCM Highway.
ASLIC/ASLAC Products
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM79213.PDF ] | |
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