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PDF CS4630 Data sheet ( Hoja de datos )
| Número de pieza | CS4630 | |
| Descripción | CrystalClear SoundFusion PCI Audio Accelerator | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS4630
CrystalClear™ SoundFusion® PCI Audio Accelerator
Features
l 420 MIPs SLIMD™ DSP Architecture with
increased internal memory for greater
performance
l Hardware acceleration for Microsoft
DirectSound® and DirectSound3D®
Positional Audio
l Sensaura™ 3-D, 2 or 4 channel audio
l EAX™ 1.0 enhanced environmental audio
standard
l Unlimited-Voice Wavetable Synthesis with
Effects including DLS support
l Acoustic Echo Cancellation Hardware
Acceleration for NetMeeting™
l 10 Band Graphic Equalization
l High Quality Hardware Sample Rate
Conversion (90+ dB Dynamic Range)
l PC/PCI, DDMA, and CrystalClear Legacy
Support (CCLS™)
l PCI 2.1 Compliant PCI Interface
l Full duplex, 128 Stream DMA Interface with
Hardware Scatter/Gather Support
l PCI Power Management (D0 through
D3cold), APM 1.2, and ACPI 1.0
l Power Management Event (PME#)
Generation within D0-D3cold
l Dual AC ‘97 2.1 Codec Interface
l Asynchronous Digital Serial
Interface (ZV Port)
l S/PDIF Digital Input and Output
support for PCM and AC3
encoded 5.1 Channel Formats
l DirectInput™ Joystick and MPU-
401 MIDI In/Out
PCI
Interface
l 3.3 V / 2.5 V Power Supply (5 V
tolerant I/O)
l PC 98 and PC 99 Compliant
Description
The CS4630 is a high performance upgrade to the
CS4624 PCI audio accelerator. With support for legacy
compatibility modes, the CS4630 enables real mode
DOS compatibility within PCI-only audio subsystems.
This device, combined with application and driver
software, provides a complete system solution for
hardware acceleration of Microsoft’s DirectSound,
DirectSound3D, DirectInput, and Wavetable Synthesis.
WDM drivers provide support for both Windows 98® and
Windows 2000®.
The CS4630 is based on the Cirrus Logic CrystalClear™
Stream Processor (SP) DSP core. The SP core is
optimized for digital audio processing, and is powerful
enough to handle complex signal processing tasks such
as Sensaura 3D, 4-channel output, and hardware
wavetable synthesis. The SP core is supported by a bus
mastering PCI interface and a built-in dedicated DMA
engine with hardware scatter-gather support. These
support functions ensure extremely efficient transfer of
audio data streams to and from host-based memory
buffers, providing a system solution with maximum
performance and minimal host CPU loading.
ORDERING INFORMATION
CS4630-CM 128-pin MQFP 14x20x2.85 mm
128-Stream
DMA Controller
with Hardware
Scatter/Gather
PC/PCI &
CCLS Legacy
MPU-401
MIDI Interface
Joystick
In te rfa c e
Parameter
RAM
Sample
RAM
Program SLIMD
RAM SP Core
Program
ROM
Coefficient
ROM
Dual Codec
AC ’97 2.1
Interface
EGPIO
S/PDIF In
S/PDIF Out
ZV Port
Async. Serial
Port Interface
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 1999
(All Rights Reserved)
NOV ‘99
DS445PP1
1
1 page  
CS4630
AC CHARACTERISTICS (PCI SIGNAL PINS ONLY) (TA = 0° to 70° C;
PCIVDD = CRYVDD = 3.3 V; CVDD = 2.5 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V;
Logic 0 = 0 V, Logic 1 = 3.3 V; Reference levels = 1.4 V; unless otherwise noted; (Note 4))
Parameter
Switching Current High
(Note 5)
0 < Vout < 1.4
1.4 < Vout < 2.4
Symbol
IOH
Switching Current Low
Low Clamp Current
Output rise slew rate
Output fall slew rate
3.1 < Vout < 3.3
(Note 5)
Vout > 2.2
2.2 > Vout > 0.55
0.71 > Vout > 0
-5 < Vin < -1
0.4 V - 2.4 V load
(Note 6)
2.4 V - 0.4 V load
(Note 6)
IOL
ICL
slewr
slewf
Min
-44
-
95
Vout/0.023
-
1
1
Max
-
-
Note 7
-
-
Note 8
-
5
5
Unit
mA
mA
mA
mA
mA
V/ns
V/ns
Notes: 4. Specifications guaranteed by characterization and not production testing.
5. Refer to V/I curves in Figure 1. Specification does not apply to PCICLK and RST# signals. Switching
Current High specification does not apply to SERR#, PME#, and INTA# which are open drain outputs.
6. Cumulative edge rate across specified range. Rise slew rates do not apply to open drain outputs.
7. Equation A: IOH = 11.9 * (Vout - 5.25) * (Vout + 2.45) for 3.3 V > Vout > 3.1 V
8. Equation B: IOL = 78.5 * Vout * (4.4 - Vout) for 0 V < Vout < 0.71 V
voltage
3.3
2.4
Pull Up
test
point
DC
drive point
1.4
AC drive
point
-2 -44 Current (mA) -176
Equation A:
IOH = 11.9*(Vout-5.25)*(Vout+2.45)
for 3.3V > Vout > 3.1V
voltage
3.3
Pull Down
AC drive
point
2.2
DC drive
point
0.55
3, 6
test
point
95 Current (mA) 380
Equation B:
IOL = 78.5*Vout*(4.4-Vout)
for 0V < Vout < 0.71V
DS445PP1
Figure 1. AC Characteristics
5
5 Page 
CS4630
EEPROM TIMING CHARACTERISTICS (TA = 0 to 70 °C, PCIVDD = CRYVDD = 3.3 V; CVDD =
2.5V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V;
Timing reference levels = 1.4 V; PCI clock frequency = 33 MHz; unless otherwise noted (Note 4))
Parameter
Symbol
Min
Max Units
EECLK Low to EEDAT Data Out Valid
Start Condition Hold Time
EECLK Low
EECLK High
Start Condition Setup Time (for a Repeated Start Condition)
EEDAT In Hold Time
EEDAT In Setup Time
EEDAT/EECLK Rise Time
(Note 19)
EEDAT/EECLK Fall Time
Stop Condition Setup Time
EEDAT Out Hold Time
tAA
tHD:STA
tLEECLK
tHEECLK
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tDH
0
5.0
10
10
5.0
0
250
-
-
5.0
0
7.0 µs
- µs
- µs
- µs
- µs
- µs
- ns
1 µs
300 ns
- µs
- µs
Notes: 19. Rise time on EEDAT is determined by the capacitance on the EEDAT line with all connected gates and
the required external pull-up resistor. Nominal values based on 4.7k and 22pF.
EECLK
EEDAT (IN)
t SU:STA
EEDAT (OUT)
EEDAT (OUT)
DS445PP1
t t tHEECLK
LEECLK
F
t HD:STA
t AA
t HD:DAT
t DH
t SU:DAT
Figure 6. EEPROM Timing
tR
t SU:STO
11
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