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PDF SPL11A Data sheet ( Hoja de datos )
| Número de pieza | SPL11A | |
| Descripción | SPL11A PROGRAMMING GUIDE | |
| Fabricantes | SunPlus | |
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SPL11A Programming Guide
V0.1 – Oct. 23, 2002
Technology for easy living
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information
provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS
TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS
TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third
parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical
components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the
product may reasonably be expected to result in significant injury to the user, without the express written approval
of Sunplus.
19, Innovation Road 1 • Science-Based Industrial Park • Hsin-Chu • Taiwan • R.O.C.
1 page  
PRELIMINARY
SPL11A PROGRAMMING GUIDE
Revision
Date
1 Revision History
By Remark
Sunplus Technology Co., Ltd.
PAGE 5
V0.1 – OCT. 23, 2002
5 Page 
PRELIMINARY
SPL11A PROGRAMMING GUIDE
4 CPU Clock Control
4.1 Clock Source Control
There are two groups of clock sources controlled by two clock option pins:
1. High-speed clock sources (HSCK): PLL / ROSC.
2. Low-speed clock sources (LSCK): 32768Hz oscillator / 32768 Crystal.
They are selected by pin option (OTP version) or mask option (ROM version). In OTP version: HSCK
(High-speed clock) can be selected to PLL or Rosc via HCKOPT pin (pull-high for PLL; pull-low for
ROSC (default)). In ROM version: HSCK (High-speed clock) can be selected to PLL or Rosc via mask
option.
In OTP version: LSCK (Low-speed clock) can be selected to X32K or R32K by LCKOPT pin (pull high
for R32K; pull-low for X32K (default)). In ROM version: LSCK (Low-speed clock) can be selected to
X32K or R32K via mask option.
4.1.1 Clock sources combination (OTP)
HCKOPT
LCKOPT
ROSC/X32K
0
0
ROSC/R32K
0
1
PLL/X32K
1X
Note: No PLL/R32K combination, it is mapped to PLL/X32K mode
Note
4.2 CPU Clock Control Register
4.2.1 P_05H_CPU_CLK ($0005): set CPU clock
$0005 b7 b6 b5 b4
Name
-
-
-
-
R/W - - - -
Default
-
-
-
-
b3 b2 b1 b0
- CPUCK2 CPUCK1 CPUCK0
- R/W R/W R/W
- 000
Bit
Mode
CPUCK=HSCK/16
CPUCK=HSCK/8
CPUCK=HSCK/4
CPUCK=HSCK/2
CPUCK=LSCK(32768)
b2
(CPUCK2)
0
0
0
0
1
b1
(CPUCK1)
0
0
1
1
X
b0
(CPUCK0)
0
1
0
1
X
Sunplus Technology Co., Ltd.
PAGE 11
V0.1 – OCT. 23, 2002
11 Page | ||
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| PDF Descargar | [ Datasheet SPL11A.PDF ] | |
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