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PDF SPL61A Data sheet ( Hoja de datos )
| Número de pieza | SPL61A | |
| Descripción | 80KB LCD Controller/Driver | |
| Fabricantes | SunPlus | |
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SPL61A
80KB LCD Controller/Driver
AUG. 13, 2001
Version 1.2
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO.
is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document.
Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by
SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may
reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
1 page  
SPL61A
5. FUNCTIONAL DESCRIPTIONS
5.1. ROM Area
SPL61A is a large ROM based micro-controller with 640 dots LCD
driver. The large ROM can be defined as program ROM, LCD
fonts and audio data continuously without any limitation. To
access the ROM area, users should first program the BANK
SELECT Register ($07) and then access the bank#1 or bank#2 by
addressing the higher bank address, $8000 - $FFFF, to fetch
data.
In operating state, all modules (CPU, 32768 oscillator,
timer/counter, LCD driver…) are activated. The halt/standby
state is entered by writing to SLEEP register ($09). There are
four wake-up sources in SPL61A: port IOEF wake-up, TIMR0
wake-up, 4Hz/8Hz/16Hz/32Hz wake-up and 2Hz/1Hz wake-up. If
any wake-up event occurs, execution of the next instruction
continues in the operating state.
5.2. Map of Memory and I/Os
*I/O PORT:
* MEMORY MAP
― PORT IOAB $0002
$00000
― PORT IOCD $0003
― PORT IOEF $0004
― I/O AB_CTRL $0001
― I/O CD_CTRL $0000
― I/O EF_CTRL $0006
*NMI SOURCE:
― INT1 ( from TIMER 1 )
*INT SOURCE:
― INT0 ( from TIMER 0 )
― INT1 ( from TIMER 1 )
― 2 KHz
― T2 Hz ( 2Hz / 1 Hz)
$0003F
$00040
$000FF
$00100
$0022F
$00300
$0037F
$00400
$007FF
$00800
$07FFF
$08000
$0FFFF
$10000
H/W registers , I/Os
WORKING SRAM(192 bytes)
SRAM for STACK and
Data Storage (304bytes)
LCD Buffer ( 80 bytes)
SUNPLUS TEST PROGRAM
USER's PROGRAM
DATA AREA
ROM BANK
ROM BANK #1
― T16 Hz ( 4Hz/8Hz/16Hz/32Hz )
― 128 Hz
― EXT INT ( from IOCD0 pin )
― UART
$13FFF
$14000
$17FFF
UNUSED
ROM BANK #2
Note: $7FFA - $7FFF in ROM bank#0, and $FFFA - $FFFF in bank#1 - 2
are reserved for reset vectors.
$7FF2 - $7FF7 in bank#0, and $FFF2 - $FFF7 in bank#1 - 2 are
reserved for testing.
5.3. Operating States
The SPL61A supports three operating states: standby, halt, and
operating. Following table shows the differences between the
three operating states.
CPU
32768 oscillator
LCD driver
Operating
ON
ON
ON
Halt
OFF
ON
ON/OFF
Standby
OFF
OFF
OFF
When in standby, all modules will be shut down, and RAM and
I/Os remain in their previous states. The current consumption is
minimized in standby. By writing to SLEEP register but keeps
32768 oscillator running, the system is in halt state. In halt state,
CPU clock is halted while it waits for an event (key press, timer
overflow) to generate a wake-up. The 32768 related modules
(timer/counter, LCD driver…) may remain active in the halt state.
Following figure is a state diagram for the SPL61A.
OPERATING
Write to SLEEP register,
32768 oscillator OFF
Wake-up or user reset
STANDBY
HALT
State Diagram of SPL61A
5.4. Speech and Melody
Since SPL61A provides large ROM and wide range of CPU
operating speed, it is the most appropriate IC for speech and
melody synthesis. For speech synthesis, SPL61A provides
several timer interrupts for precise sampling frequency. Users
can record or synthesize the sound and digitize it into the ROM.
The sound then can be played back in the sequence assigned by
users’ programs. Several algorithms are recommended for high
fidelity and good compression of sound: such as PCM and
ADPCM.
For melody synthesis, SPL61A provides the dual tone mode.
Once in the dual tone mode, users only need to program the tone
frequency of each channel by writing to timer/counter TM0 and
TM1, and set the envelope of each channel. The hardware will
toggle the tone wave automatically without users’ care.
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
5
AUG. 13, 2001
Version: 1.2
5 Page 
7.3. Serial Communications between two SPL61As
VDD
VDD
R
VDD
TxD
SPL61A
VSS
RxD
SPL61A
VDD
R
VDD
RxD VDD
SPL61A
TxD VSS
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
11
AUG. 13, 2001
Version: 1.2
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet SPL61A.PDF ] | |
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