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PDF AT73C213 Data sheet ( Hoja de datos )
| Número de pieza | AT73C213 | |
| Descripción | Power Management for Mobiles (PM) / Audio Interface for Portable Handsets | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Stereo Audio DAC
– 2.7V to 3.3V Analog Supply Operation
– 2.4V to 3.3V Digital Supply Operation
– 20-bit Stereo Audio DAC
– 93 dB SNR Playback Stereo Channels
– 32 Ohm/20 mW Stereo Headset Drivers with Master Volume and Mute Controls
– Stereo Line Level Input with Volume Control/mute and Playback through the
Headset Drivers
– Differential Monaural Auxiliary Input, with Volume Control/mute and Playback
through the Headset Drivers
– Accepts Mixed Signals from All Signal Paths (Line Inputs, External Mono and DAC
Output)
– 8, 11.024, 16, 22.05, 24, 32, 44.1 and 48 kHz Sampling Rates
– 256x or 384xFs Master Clock Frequency
– I2S Serial Audio Interface
• Mono Audio Power Amplifier
– Supply Input from Main Li-Ion Battery
– 440mW on 8 Ohm Load
– Low Power Mode for Earphone
– Programmable Volume Control (-22 to +20 dB)
– Fully Differential Structure, Input and Output
– 8 mA Drain Current in Full Power Mode
– Power-down mode (Consumption Less than 2uA)
– Minimum External Components (Direct Connection of the Loudspeaker)
• Applications: Mobile Phones, Digital Cameras, PDAs, SmartPhones, DECT Phones,
Music Players
Power
Management for
Mobiles (PM)
AT73C213
Audio Interface
for Portable
Handsets
1. Description
The AT73C213 is a fully integrated, low-cost, combined stereo audio DAC and audio
power amplifier circuit targeted for Li-Ion or Ni-Mh battery powered devices such as
mobile phones, smartphones, PDA, DECT phones, digital still cameras, music players
or any other type of handheld device where an audio interface is needed.
The stereo DAC section is a complete high performance, stereo audio digital-to-ana-
log converter delivering a 93 dB dynamic range. It comprises a multibit sigma-delta
modulator with dither, continuous time analog filters and analog output drive circuitry.
This architecture provides a high insensitivity to clock jitter. The digital interpolation fil-
ter increases the sample rate by a factor of 8 using 3 linear phase half-band filters
cascaded, followed by a first order SINC interpolator with a factor of 8. This filter elim-
inates the images of baseband audio, retaining only the image at 64x the input sample
rate, which is eliminated by the analog post filter. Optionally, a dither signal can be
added that reduces possible noise tones at the output. However, the use of a multibit
sigma-delta modulator already provides extremely low noise tone energy.
Master clock is from 256 or 384 times the input data rate, allowing choice of input data
rate up to 50 kHz, including standard audio rates of 48, 44.1, 32, 16 and 8 kHz.
The DAC section is followed by a volume and mute control and can be simultaneously
played back directly through a stereo 32 Ohm headset pair of drivers.
2744A–PMGMT–27-Jan-05
1 page  
Table 6-1. Audio Power Amplifier Electrical Specifications
Parameter Symbol
Conditions
BWmin
Low Frequency Cutoff
1 kHz reference frequency
3 dB attenuation
470 nF input coupling capacitors
BWmax
High Frequency Cutoff
1 KHz reference frequency
3 dB attenuation
470 nF input coupling capacitors
tUP Output setup time
Off to on mode
Voltage already settled
Input capacitors precharged
VN
THDHP
Output noise
Output distortion
Max gain, A weighted
High power mode, VDD = 3.6V, 1 kHz,
Pout = 100 mW, gain = 0dB
THDLP
Output distortion
Low power mode, VDD = 3.6V, 1KHz,
Vout = 100m Vpp, Max gain, load 8
ohms in series with 200 ohms
Pmax
Maximum power
Low power mode, VDD = 3.6V, 1 KHz,
Vout = 100 mVpp, Max gain, load 8
ohms in series with 200 ohms
GACC
GSTEP
Overall Gain accuracy
Gain Step Accuracy
AT73C213
Min Typ Max Unit
50 Hz
20 kHz
10 ms
120 500 µVRMS
0.3 %
1%
440 mW
-2 0 2 dB
-0.7 0 0.7 dB
2744A–PMGMT–27-Jan-05
5
5 Page 
7.4 Timing Specifications
Figure 7-7.
Data Interface Timing Diagram
1N
MCLK
td1
BCLK
1
19N+1
20N
20
td2
LRFS
ts3 th3
SDIN
M/2.N+1 M/2.(N+1) (M-1).N+1 M.N
M/2+1
M
AT73C213
Table 7-2.
td1
td2
ts3
th3
Data Interface Timing Parameters
Parameter
Delay from MCLK rising edge to BCLK edges
Delay from BCLK falling edge to LRFS edges
din set-up time before BCLK rising edge
din hold time after BCLK rising edge
Min Typ Max Unit
2.5 7.5 ns
0 5 ns
10 ns
10 ns
2744A–PMGMT–27-Jan-05
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT73C213.PDF ] | |
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