PDF MT9040 Data sheet ( Hoja de datos )

Número de pieza	MT9040
Descripción	T1/E1 Synchronizer
Fabricantes	Zarlink Semiconductor
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No Preview Available ! MT9040 T1/E1 Synchronizer Features • Supports AT&T TR62411 and Bellcore GR-1244- CORE and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces • Selectable 19.44 MHz, 1.544MHz, 2.048MHz or 8kHz input reference signals • Provides C1.5, C2, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals • Provides 5 different styles of 8 KHz framing pulses • Attenuates wander from 1.9Hz • Fast lock mode • JTAG Boundary Scan Applications • Synchronization and timing control for multitrunk T1 and E1 systems • ST-BUS clock and frame pulse source Data Sheet November 2003 Ordering Information MT9040AN 48 pin SSOP -40°C to +85°C Description The MT9040 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links. The MT9040 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048MHz, 1.544MHz, or 8kHz input reference. The MT9040 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE, Stratum 4; and ETSI ETS 300 011. It will meet the jitter/wander tolerance, jitter transfer, intrinsic jitter, frequency accuracy and capture range for these specifications. OSCi OSCo FLOCK LOCK VDD VSS TCK TDI TMS TRST TDO REF Master Clock IEEE 1149.1a Control State Machine DPLL Input Impairment Monitor Output Interface Circuit Feedback Frequency Select MUX C19o C1.5o C2o C4o C6o C8o C16o F0o F8o F16o RSP TSP MS RST IM FS1 FS2 Figure 1 - Functional Block Diagram Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912, France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. 1 page MT9040 Data Sheet Reference Phase Detector Loop Filter Digitally Controlled Oscillator DPLL Reference to Output Interface Circuit Feedback Signal from Frequency Select MUX State Select from Input Impairment Monitor Control Circuit State Select from State Machine Figure 3 - DPLL Block Diagram Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four reference frequency selections (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). This filter ensures that the network jitter transfer requirements are met. Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input Impairment Circuit to set the mode of the DPLL. The two possible modes are Normal and Freerun. Digitally Controlled Oscillator (DCO) - the DCO receives the filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the MT9040. In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the input reference sinal. In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source. Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical to the line frequency), and the input phase offset is small, then the lock signal will be set high. For specific Lock Indicator design recommendations, see the Applications - Lock Indicator section. Output Interface Circuit The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure 4. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1 Divider Circuit, and a DS2 Divider Circuit to generate the required output signals. Four tapped delay lines are used to generate 16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz signals. The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and five frame pulse outputs. The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively. These outputs have a nominal 50% duty cycle. The T1 Divider Circuit uses the 12.384MHz signal to generate the C1.5o clock by dividing the internal C12 clock by eight. This output has a nominal 50% duty cycle. The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal 50% duty cycle. 5 Zarlink Semiconductor Inc. 5 Page MT9040 Data Sheet MT9040 OSCi 1MΩ 20MHz 56pF 39pF 3-50pF OSCo 100Ω 1uH 1uH inductor: may improve stability and is optional Figure 6 - Crystal Oscillator Circuit The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. Typically, for a 20MHz crystal specified with a 32pF load capacitance, each 1pF change in load capacitance contributes approximately 9ppm to the frequency deviation. Consequently, capacitor tolerances, and stray capacitances have a major effect on the accuracy of the oscillator frequency. The trimmer capacitor shown in Figure 6 may be used to compensate for capacitive effects. If accuracy is not a concern, then the trimmer may be removed, the 39pF capacitor may be increased to 56pF, and a wider tolerance crystal may be substituted. The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal specification is as follows. Frequency: 20MHz Tolerance: As required Oscillation Mode: Fundamental Resonance Mode: Parallel Load Capacitance: 32pF Maximum Series Resistance: 35Ω Approximate Drive Level: 1mW e.g., R1B23B32-20.0MHz (20ppm absolute, ±6ppm 0C to 50C, 32pF, 25Ω) 11 Zarlink Semiconductor Inc. 11 Page

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