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PDF MT90810 Data sheet ( Hoja de datos )
| Número de pieza | MT90810 | |
| Descripción | CMOS Flexible MVIP Interface Circuit | |
| Fabricantes | Mitel Networks Corporation | |
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CMOS MT90810
®
Flexible MVIP Interface Circuit
Preliminary Information
Features
• MVIP™ and ST-BUS™ compliant
• MVIP Enhanced Switching with 384x384
channel capacity (256 MVIP channels; 128
local channels)
• On-chip PLL for MVIP master/slave operation
• Local output clocks of 2.048,4.096,8.192MHz
with programmable polarity
• Local serial interface is programmable to
2.048, 4.096, or 8.192Mb/s with associated
clock outputs
• Additional control output stream
• Per-channel message mode
• Two independently programmable groups of up
to 12 framing signals each
• Motorola non-multiplexed or Intel multiplexed/
non-multiplexed microprocessor interface
•
Applications
• Medium size digital switch matrices
• MVIP interface functions
• Serial bus control and monitoring
• Centralized voice processing systems
• Voice/Data multiplexer
ISSUE 2
October 1994
Ordering Information
MT90810AK 100 Pin PQFP
0 °C to +70 °C
Description
Mitel’s MT90810 is a Flexible MVIP Interface Circuit
(FMIC). The MVIP (Multi-Vendor Integration
Protocol) compliant device provides a complete
MVIP compliant interface between the MVIP Bus and
a wide variety of processors, telephony interfaces
and other circuits. A built-in digital time-slot switch
provides MVIP enhanced switching between the full
MVIP Bus and any combination of up to 128 full
duplex local channels of 64kbps each. An 8 bit
microprocessor port allows real-time control of
switching and programming of device configuration.
On-board clock circuitry, including both analog and
digital phase-locked loops, supports all MVIP clock
modes. The local interface supports PCM rates of
2.048, 4.096 and 8.192Mb/s, as well as parallel DMA
through the microprocessor port.
SEC8K
C4b
C2o
F0b
DSo[0:7]
DSi[0:7]
LDO[0:3]
LDI[0:3]
TCK
TMS
TDI
TDO
EX_8KA EX_8KB X2 X1/CLKIN PLL_LO PLL_LI FRAME
S-P/
P-S
Timing and Clock Control
(Oscillator and Analog & Digital PLLs)
Enhanced Switch
Data Memory
Connection Memory
Programmable
Framing Signals
JTAG
Microprocessor Interface
CLK2
CLK4
CLK8
RESET
CSTo
FGA[0:11]
FGB[0:11]
ERR
AD[0:7] A[0:1] ALE WR/ RD/ CS RDY/ DREQ[0:1] DACK[0:1]
R/W DS
DTACK
Figure 1 - Functional Block Diagram
2-145
1 page  
Preliminary Information
MT90810
Pin Description
Pin #
12
13
17
18
22
23
21
24
15, 40, 65, 86
16, 41, 52, 66,
79, 93
Name
TDO
TMS
X1/CLKIN
X2
PLL_LO
PLL_LI
VCO_VSS
VCO_VDD
VDD[0:3]
VSS[0:5]
Description
JTAG Serial Output Data (Output). If not used, this pin should be left
unconnected.
JTAG Mode Control Input (TTL Input). If not used, this pin should be
left unconnected.
Clock Input Pin/ Crystal Oscillator Pin1.
Crystal Oscillator Pin 2 (Input). If X1 is clock input, this pin should be
left unconnected.
PLL Loop Filter Output. (Output 6mA drive).
PLL Loop Filter Input. (1 µA Low level/High level Input current).
Ground for On-chip VCO.
+5 Volt Power Supply for On-chip VCO.
+5 Volt Power Supply.
Ground.
Device Overview
Mitel’s MT90810 is a MVIP compliant device. It
provides a complete, cost effective, MVIP compliant
interface between the MVIP Bus and a wide variety
of processors, telephony interfaces and other
circuits. The FMIC supports 384 full duplex, time
division multiplexed (TDM), channels. These
channels are divided into 256 full duplex MVIP
channels and 128 full duplex local channels. The
sample rate for each channel is 8kHz and the width
of each channel is 8 bits for a total data rate of
64kbits/s per channel.
The FMIC’s internal clock circuitry includes both an
analog and a digital PLL and supports all MVIP clock
modes. The device can be configured as a timing
master whereby an external 16.384MHz crystal or
4.096, 8.192 or 16.384MHz external clock source is
used to generate MVIP clock signals. The device can
also operate as a slave to the MVIP bus,
synchronizing its master clock to the MVIP 4MHz
bus clock.
The device’s local serial interface supports PCM
rates of 2.048, 4.096 and 8.192Mb/s, per channel
message mode, an additional control stream, as well
as parallel DMA through the microprocessor port.
Furthermore, the FMIC’s programmable group of
output framing signals and local output clocks may
be used to provide the appropriate frame and clock
pulses to drive other local serial buses such as GCI.
A microprocessor interface permits reading and
writing of the data memory, connection memory and
all internal control registers. The Connection and
Data memory can be read and updated while the
MVIP bus is active, that is, connections can be made
without interrupting bus activities.
Functional Description
Switching
The FMIC provides for switching of data from any
input channel to any output channel. This is
accomplished by buffering a single sample of each
channel in an on-chip 384 byte static RAM. Samples
are written into this data RAM in a fixed order and
read out in an order determined by the programming
of the connection memory. An input shift register and
holding latch for each input stream make up the
serial to parallel conversion blocks on the input of
the FMIC and an output holding register an shift
register make up the parallel to serial conversion
blocks on the output of the FMIC.
Data Memory
Data memory is a 384 byte static RAM block which
provides one sample of buffering for each of the 384
channels. An input shift register and holding latch for
each input stream make up the serial to parallel
conversion blocks on the input. Each input channel is
mapped to a unique location in the RAM, as shown
Table 18 - “Data Memory Mapping”.
Data memory can be read and written by the
microprocessor (See “Software Control” for further
details). Note that writing to data memory may be
futile since the contents will be overwritten by
incoming data on the serial input streams.
2-149
5 Page 
Preliminary Information
MT90810
memory and auto increment/decrement mode is
written to the AMR. Finally, the write operation is
performed when data is written to the Indirect Data
Register(IDR). Similarly, to perform a read operation
from an indirect location, the LAR and AMR must be
initialized and then the data can be read from the
IDR.
Data memory can be read and written by the
microprocessor. This is accomplished by first
initializing the LAR and AMR register to select data
memory and then either reading from or writing to
the Indirect Data Register.
Connection memory can be read and written by the
microprocessor. This is accomplished by first
initializing the LAR and AMR register to select high
or low connection memory and then either reading
from or writing to the IDR.
The indirect address can be programmed to auto-
increment after reads or writes to the indirect data
register by setting bits 6 and 7 in the AMR
accordingly. The auto-increment occurs only when
the indirect address register points to either data
memory or the high byte of connection memory.
If auto-increment on read/write is enabled, and
connection memory is selected, then consecutive
reads/writes to the IDR will toggle between selection
of low to high then back to low byte of connection
memory and continue on toggling until the reads/
writes to IDR stop. Note that when reading/writing
connection memory with auto increment disabled,
the reads/writes to IDR will toggle from low to high
byte connection memory once only.
Using the auto-increment feature, the connection
memory can be quickly initialized by resetting the
LAR and initializing the AMR for auto-increment on
write with connection memory low byte selected.
Writing a stream of bytes to IDR will then fill
connection memory. The first byte written to the IDR
will go to the low byte of the first connection memory
location. The memory space selection will be
automatically toggled to select connection memory
high. The second byte written to the IDR will then be
written to connection memory high of the first
connection memory location. The memory space will
automatically toggle back to the low byte connection
memory and the address pointer will be incremented
to prepare for writing to the next location in
connection memory. Similarly, the contents of
connection memory can also be read back quickly by
setting the auto-increment on read bit of AMR and
reading from the IDR continuously.
Writing to a data memory of connection memory
when the address register contains an indirect RAM
address of greater than 383 will cause unpredictable
results.
DMA Interface
The DMA interface to the FMIC is accessible only
when the microprocessor interface is in INTEL mode.
All 128 local channels can be DMA’ed out to/in from
external memory. MVIP channels can be DMA’ed by
switching to local channels.
The DMA_EN bit in the FMIC Control/Status register
enables DMA mode. This bit should be set only after
the desired local channels have been enabled for
DMA. The DMA_EN bit does not take effect until
after the beginning of the next MVIP frame. This
assures that when the DMA transactions begin, that
they begin on a frame boundary.
An individual local channel is enabled for DMA by
setting the CE bit in connection memory high for that
channel. When a channel is enabled for DMA, both
input and output are enabled for DMA. The local
output data is also driven out on the programmed
serial output stream. It is not possible to enable input
without output or vice versa. If channels in time slot
0 are enabled for DMA, there will be no DMA
requests for those channels in the first frame after
DMA is enabled. Instead, setup and preparation for
the DMA will occur in that first frame, in the timeslot
preceding. DMA transfer will actually occur in the
second frame after DMA is enabled. It is, therefore,
recommended that channels in time slot 0 not be
enabled for DMA.
The DMA signals DREQ[1] and DACK[1] control
transfers for DMA reads from the FMIC while
DREQ[0] and DACK[0] control transfers for DMA
writes to the FMIC. For every 2Mb/s timeslot where a
channel is enabled for DMA, the FMIC will assert
DREQ and wait for a DACK from an external
controller. Upon receiving the acknowledgement,
DACK, it would proceed with one DMA burst transfer.
DMA read requests always occur at the beginning of
the 2Mb/s time slot during which, all channels
enabled for DMA in the timeslot will be DMA’ed out in
a burst, onto the local serial data stream. One burst
implies one DREQ cycle, whereby DREQ is held low
for the duration of the transfer. The maximum
number of 8 bit channels that can be DMA’ed out
during one burst is 4, since, regardless of the serial
interface mode, there can be only four 8 bit channels
per 2Mb/s time slot, whether it be one channel per
stream (on 4 streams) at 2Mb/s, 2 channels per
stream (on 2 streams) at 4Mb/s or 4 channels all on
one stream at 8Mb/s.
DMA write requests occur at the end of the 2Mb/s
time slot during which, all channels enabled for DMA
in the timeslot will be DMA’ed from the local serial
data stream. DMA write requests can also occur in
bursts of up to four 8 bit channels. The data for write
requests is actually staggered by one DMA request
for each stream. This means that the data written
2-155
11 Page | ||
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| PDF Descargar | [ Datasheet MT90810.PDF ] | |
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