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PDF CY8C24223A Data sheet ( Hoja de datos )
| Número de pieza | CY8C24223A | |
| Descripción | (CY8C24123A / CY8C24223A / CY8C24423A) PSoC Mixed-Signal Array | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PSoC™ Mixed-Signal Array
CY8C24123A,
CY8C24223A, and CY8C24423A
Final Data Sheet
Features
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 2.4 to 5.25 V Operating Voltage
❐ Operating Voltages Down to 1.0V Using On-
Chip Switch Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■ Advanced Peripherals (PSoC Blocks)
❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
❐ 4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Oscillator
❐ High-Accuracy 24 MHz with Optional 32 kHz
Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
■ Flexible On-Chip Memory
❐ 4K Bytes Flash Program Storage 50,000
Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP™)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
❐ Up to 10 Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
■ New CY8C24x23A PSoC Device
❐ Derived from the CY8C24x23 Device
❐ Low Power and Low Voltage (2.4V)
■ Additional System Resources
❐ I2C™ Slave, Master, and Multi-Master to
400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software
(PSoC™ Designer)
❐ Full-Featured, In-Circuit Emulator and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
PSoC CORE
Port 2
Port 1
Port
0
Analog
Drivers
System Bus
Global Digital Interconnect
Global Analog Interconnect
SRAM
256 Bytes
Interrupt
Controller
SROM Flash 4K
CPU Core (M8C)
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
(1 Row,
4 Blocks)
ANALOG SYSTEM
Analog
Block
Array
Analog
Ref
(2 Columns,
6 Blocks)
Analog
Input
Muxing
Digital
Clocks
Multiply
Accum.
Decimator
POR and LVD
I2C
System Resets
SYSTEM RESOURCES
Internal
Voltage
Ref.
Switch
Mode
Pump
PSoC™ Functional Overview
The PSoC™ family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C24x23A family can have up to three IO
ports that connect to the global digital and analog interconnects,
providing access to 4 digital blocks and 6 analog blocks.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
September 8, 2004
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12028 Rev. *B
1
1 page  
CY8C24x23A Final Data Sheet
PSoC™ Overview
PSoC Designer Software Subsystems
Device Editor
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configu-
ration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
a given project configuration for use during application pro-
gramming in conjunction with the Device Data Sheet. Once the
framework is generated, the user can add application-specific
code to flesh out the framework. It’s also possible to change the
selected components and regenerate the framework.
Design Browser
The Design Browser allows users to select and import precon-
figured designs into the user’s project. Users can easily browse
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tools include a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, com-
pile, link, and build.
Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries auto-
matically use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports Cypress MicroSystems’ PSoC family devices.
Even if you have never worked in the C language before, the
product quickly allows you to create complete C programs for
the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is avail-
able for development support. This hardware has the capability
to program single devices.
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
will operate with all PSoC devices. Emulation pods for each
device family are available separately. The emulation pod takes
the place of the PSoC device in the target board and performs
full speed (24 MHz) operation.
September 8, 2004
Document No. 38-12028 Rev. *B
5
5 Page 
CY8C24x23A Final Data Sheet
1.1.4 32-Pin Part Pinout
Table 1-4. 32-Pin Part Pinout (MLF*)
Pin Type
Pin
No. Digital Analog Name
Description
1 IO
P2[7]
2 IO
P2[5]
3 IO
I P2[3] Direct switched capacitor block input.
4 IO
I P2[1] Direct switched capacitor block input.
5
Power
Vss Ground connection.
6
Power
SMP Switch Mode Pump (SMP) connection to
external components required.
7 IO
P1[7] I2C Serial Clock (SCL)
8 IO
P1[5] I2C Serial Data (SDA)
9 NC No connection. Do not use.
10 IO
P1[3]
11 IO
P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
12
Power
Vss Ground connection.
13 IO
P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA)
14 IO
P1[2]
15 IO
P1[4] Optional External Clock Input (EXTCLK)
16 NC No connection. Do not use.
17 IO
P1[6]
18
Input
XRES Active high external reset with internal pull
down.
19 IO
I P2[0] Direct switched capacitor block input.
20 IO
I P2[2] Direct switched capacitor block input.
21 IO
P2[4] External Analog Ground (AGND)
22 IO
P2[6] External Voltage Reference (VRef)
23 IO
I P0[0] Analog column mux input.
24 IO
I P0[2] Analog column mux input.
25 NC No connection. Do not use.
26 IO
I P0[4] Analog column mux input.
27 IO
I P0[6] Analog column mux input.
28
Power
Vdd Supply voltage.
29 IO
I P0[7] Analog column mux input.
30 IO
IO P0[5] Analog column mux input and column output.
31 IO
IO P0[3] Analog column mux input and column output.
32 IO
I P0[1] Analog column mux input.
LEGEND: A = Analog, I = Input, and O = Output.
* The MLF package has a center pad that must be connected to ground (Vss).
1. Pin Information
CY8C24423A 32-Pin PSoC Device
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
Vss
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
1
2
3
4
5
6
7
8
MLF
(Top View)
24 P0[2], AI
23 P0[0], AI
22 P2[6], External VRef
21 P2[4], External AGND
20 P2[2], AI
19 P2[0], AI
18 XRES
17 P1[6]
September 8, 2004
Document No. 38-12028 Rev. *B
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY8C24223A.PDF ] | |
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