PDF K4H560838F-TC Data sheet ( Hoja de datos )

Número de pieza	K4H560838F-TC
Descripción	DDR SDRAM 256Mb F-die
Fabricantes	Samsung Semiconductor
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No Preview Available ! DDR SDRAM 256Mb F-die (x8, x16) DDR SDRAM 256Mb F-die DDR SDRAM Specification Revision 1.1 Rev. 1.1 August. 2003 1 page DDR SDRAM 256Mb F-die (x8, x16) Package Physical Dimension #66 #34 DDR SDRAM Units : Millimeters #1 (1.50) (R0.15) (0.71) NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS’Y OUT QUALITY (10×) (10×) #33 0.125 +0.075 -0.035 22.22±0.10 0.65TYP 0.65±0.08 (10×) 0.30±0.08 (10×) 0.10 MAX [ 0.075 MAX ] 0.25TYP 0×~8× 66pin TSOPII / Package dimension Rev. 1.1 August. 2003 5 Page DDR SDRAM 256Mb F-die (x8, x16) DDR SDRAM < Detailed test conditions for DDR SDRAM IDD1 & IDD7A > IDD1 : Operating current: One bank operation 1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 2. Timing patterns - B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3tCK, tRC = 9tCK, tRAS = 6tCK Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst - A2 (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3tCK, tRC = 9tCK, tRAS = 6tCK Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst - AA (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 2tCK, tRC = 8tCK, tRAS = 6tCK Read : A0 N R0 N N N P0 N A0 N - repeat the same timing with random address changing 50% of data changing at every burst - B3(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3tCK, tRC = 10tCK, tRAS=7tCK Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP IDD7A : Operating current: Four bank operation 1. Typical Case : Vdd = 2.5V, T=25’ C 2. Worst Case : Vdd = 2.7V, T= 10’ C 3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4. Timing patterns - B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2tCK, tRCD = 3tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 100% of data changing at every burst - A2(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2tCK, tRCD = 3tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 100% of data changing at every burst - AA (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 2tCK, tRC = 8tCK, tRAS = 6tCK Read : A0 N R0 N N N P0 N A0 N - repeat the same timing with random address changing 50% of data changing at every burst - B3(166Mhz,CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRRD=2tCK, tRCD=3tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *100% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP Rev. 1.1 August. 2003 11 Page

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