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PDF MC74VHCT50A Data sheet ( Hoja de datos )
| Número de pieza | MC74VHCT50A | |
| Descripción | Noninverting Buffer / CMOS Logic Level Shifter with LSTTL-Compatible Inputs | |
| Fabricantes | ON Semiconductor | |
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MC74VHCT50A
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
The MC74VHCT50A is a hex noninverting buffer fabricated with
silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The internal circuit is composed of three stages, including a buffered
output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic–level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic
to 3.0 V CMOS Logic while operating at the high–voltage power
supply.
The MC74VHCT50A input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHCT50A to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
• High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
• Low Power Dissipation: ICC = 2 µA (Max) at TA = 25°C
• TTL–Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
• CMOS–Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
• Power Down Protection Provided on Inputs and Outputs
LOGIC DIAGRAM
A1 1
2 Y1
A2 3
4 Y2
5
A3
A4 9
6
Y3
Y=A
8 Y4
11
A5
10
Y5
A6 13
12 Y6
LOGIC SYMBOL
A1 1 Y1
A2 1 Y2
A3 1 Y3
A4 1 Y4
A5 1 Y5
A6 1 Y6
http://onsemi.com
14–LEAD SOIC
D SUFFIX
CASE 751A
14–LEAD TSSOP
DT SUFFIX
CASE 948G
14–LEAD SOIC EIAJ
M SUFFIX
CASE 965
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
VCC A6 Y6 A5 Y5 A4 Y4
14 13 12 11 10 9 8
1234567
A1 Y1 A2 Y2 A3 Y3 GND
For detailed package marking information, see the Marking
Diagram section on page 4 of this data sheet.
ORDERING INFORMATION
Device
Package
Shipping
MC74VHCT50AD
SOIC
55 Units/Rail
MC74VHCT50ADT TSSOP
96 Units/Rail
MC74VHCT50AM SOIC EIAJ 50 Units/Rail
FUNCTION TABLE
A Input
L
H
Y Output
L
H
© Semiconductor Components Industries, LLC, 2001
July, 2001– Rev. 3
1
Publication Order Number:
MC74VHCT50A/D
1 page  
MC74VHCT50A
–A–
14
1
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
8
–B–
7
P 7 PL
0.25 (0.010) M B M
G C R X 45 _ F
–T–
SEATING
PLANE
D 14 PL
K
0.25 (0.010) M T B S A S
M
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
http://onsemi.com
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| PDF Descargar | [ Datasheet MC74VHCT50A.PDF ] | |
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