PDF MC74VHC595 Data sheet ( Hoja de datos )

Número de pieza	MC74VHC595
Descripción	8-Bit Shift Register with Output Storage Register
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8-Bit Shift Register with Output Storage Register (3-State) The MC74VHC595 is an advanced high speed 8–bit shift register with an output storage register fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC595 contains an 8–bit static shift register which feeds an 8–bit storage register. Shift operation is accomplished on the positive going transition of the Shift Clock input (SCK). The output register is loaded with the contents of the shift register on the positive going transition of the Register Clock input (RCK). Since the RCK and SCK signals are independent, parallel outputs can be held stable during the shift operation. And, since the parallel outputs are 3–state, the VHC595 can be directly connected to an 8–bit bus. This register can be used in serial–to–parallel conversion, data receivers, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. • High Speed: fmax = 185MHz (Typ) at VCC = 5V • Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C • High Noise Immunity: VNIH = VNIL = 28% VCC • Power Down Protection Provided on Inputs • Balanced Propagation Delays • Designed for 2V to 5.5V Operating Range • Low Noise: VOLP = 1.0V (Max) • Pin and Function Compatible with Other Standard Logic Families • Latchup Performance Exceeds 300mA • ESD Performance: HBM > 2000V; Machine Model > 200V • Chip Complexity: 328 FETs or 82 Equivalent Gates LOGIC DIAGRAM SERIAL DATA SI 14 INPUT SHIFT REGISTER 11 SCK 10 SCLR 12 RCK 13 OE STORAGE REGISTER 15 QA 1 QB 2 QC 3 QD 4 QE 5 QF 6 QG 7 QH PARALLEL DATA OUTPUTS 9 SQH SERIAL DATA OUTPUT MC74VHC595 D SUFFIX 16–LEAD SOIC PACKAGE CASE 751B–05 DT SUFFIX 16–LEAD TSSOP PACKAGE CASE 948F–01 M SUFFIX 16–LEAD SOIC EIAJ PACKAGE CASE 966–01 ORDERING INFORMATION MC74VHCXXXD MC74VHCXXXDT MC74VHCXXXM SOIC TSSOP SOIC EIAJ PIN ASSIGNMENT QB 1 QC 2 QD 3 QE 4 QF 5 QG 6 QH 7 GND 8 16 VCC 15 QA 14 SI 13 OE 12 RCK 11 SCK 10 SCLR 9 SQH 6/97 © Motorola, Inc. 1997 1 REV 1 1 page SWITCHING WAVEFORMS MC74VHC595 SCK 50% tw 1/fmax tPLH tPHL SQH 50% VCC Figure 1. VCC GND RCK 50% QA–QH tPLH tPHL 50% VCC Figure 3. SCLR SI SCK or RCK 50% VALID 50% tsu th 50% Figure 5. VCC GND VCC GND VCC GND VCC GND SCLR SQH SCK tw 50% tPHL 50% VCC trec 50% Figure 2. VCC GND VCC GND OE QA–QH QA–QH 50% tPZL tPLZ 50% VCC tPZH tPHZ 50% VCC Figure 4. VCC GND HIGH IMPEDANCE VOL +0.3V VOH –0.3V HIGH IMPEDANCE SCK 50% tsu(H) RCK 50% tw Figure 6. VCC GND VCC GND DEVICE UNDER TEST TEST POINT OUTPUT CL* TEST CIRCUITS DEVICE UNDER TEST TEST POINT OUTPUT 1 kΩ CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. * Includes all probe and jig capacitance Figure 7. VHC Data – Advanced CMOS Logic DL203 — Rev 1 * Includes all probe and jig capacitance Figure 8. 5 MOTOROLA 5 Page

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