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PDF MC74VHCT08A Data sheet ( Hoja de datos )
| Número de pieza | MC74VHCT08A | |
| Descripción | Quad 2-Input AND Gate | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input AND Gate
The MC74VHCT08A is an advanced high speed CMOS 2–input AND gate
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS
level output swings.
The VHCT08A input structures provide protection when voltages between
0V and 5.5V are applied, regardless of the supply voltage. The output
structures also provide protection when VCC = 0V. These input and output
structures help prevent device destruction caused by supply voltage –
input/output voltage mismatch, battery backup, hot insertion, etc.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: tPD = 4.3ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C
• TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 0.8V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 24 FETs or 6 Equivalent Gates
LOGIC DIAGRAM
1
A1
2
B1
3
Y1
4
A2
5
B2
9
A3
10
B3
6
Y2
Y = AB
8
Y3
12
A4
13
B4
11
Y4
Pinout: 14–Lead Packages (Top View)
VCC B4 A4 Y4 B3 A3 Y3
14 13 12 11 10 9 8
MC74VHCT08A
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
DT SUFFIX
14–LEAD TSSOP PACKAGE
CASE 948G–01
M SUFFIX
14–LEAD SOIC EIAJ PACKAGE
CASE 965–01
ORDERING INFORMATION
MC74VHCTXXAD
MC74VHCTXXADT
MC74VHCTXXAM
SOIC
TSSOP
SOIC EIAJ
FUNCTION TABLE
Inputs
Output
AB
Y
LL
LH
HL
HH
L
L
L
H
1234567
A1 B1 Y1 A2 B2 Y2 GND
4/99
© Motorola, Inc. 1999
1
REV 0
1 page  
MC74VHCT08A
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
0.15 (0.006) T U S
2X L/2 14
L
PIN 1
IDENT.
1
14X K REF
0.10 (0.004) M T U S V S
8
B
–U–
7
N 0.25 (0.010)
M
N
F
DETAIL E
0.15 (0.006) T U S
A
–V–
K
ÇÇÇÉÉÇÇÇÉÉÇÇÇÉÉJ J1
K1
SECTION N–N
0.10 (0.004)
–T– SEATING
PLANE
D
C
G
H DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
–W–
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC
0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
M 0_ 8_ 0_ 8_
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
5
MOTOROLA
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC74VHCT08A.PDF ] | |
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