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PDF MC74VHC373 Data sheet ( Hoja de datos )
| Número de pieza | MC74VHC373 | |
| Descripción | Octal D-Type Latch with 3-State Output | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC74VHC373 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal D-Type Latch
with 3-State Output
The MC74VHC373 is an advanced high speed CMOS octal latch with
3–state output fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
This 8–bit D–type latch is controlled by a latch enable input and an output
enable input. When the output enable input is high, the eight outputs are in a
high impedance state.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: tPD = 5.0ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 0.9V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 186 FETs or 46.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0 3
D1 4
D2 7
D3 8
D4 13
D5 14
D6 17
D7 18
2 Q0
5 Q1
6 Q2
9 Q3
12 Q4
15 Q5
16 Q6
19 Q7
NONINVERTING
OUTPUTS
LE 11
OE 1
FUNCTION TABLE
INPUTS
OE LE
D
L HH
LHL
L LX
HXX
OUTPUT
Q
H
L
No Change
Z
MC74VHC373
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
ORDERING INFORMATION
MC74VHCXXXDW SOIC
MC74VHCXXXDT TSSOP
MC74VHCXXXM
SOIC EIAJ
PIN ASSIGNMENT
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
6/97
© Motorola, Inc. 1997
1
REV 1
1 page  
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 5.
MC74VHC373
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 6.
EXPANDED LOGIC DIAGRAM
D0
3
D
Q
D1
4
D
Q
D2
7
D
Q
D3
8
D
Q
D4
13
D
Q
D5
14
D
Q
D6
17
D
Q
D7
18
D
Q
11
LE
1
OE
LE LE LE LE LE LE LE LE
2 5 6 9 12 15 16 19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
INPUT EQUIVALENT CIRCUIT
INPUT
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
5
MOTOROLA
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC74VHC373.PDF ] | |
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