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PDF SPT175 Data sheet ( Hoja de datos )
| Número de pieza | SPT175 | |
| Descripción | 8-BIT / 20 MSPS CMOS A/D CONVERTER | |
| Fabricantes | SPT | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SPT175 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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SPT1175
8-BIT, 20 MSPS CMOS A/D CONVERTER
FEATURES
• 20 MSPS Maximum Conversion Rate
• Internal Sample-and-Hold Function
• 90 mW Power Dissipation
• Internal Voltage Reference
• Single +5.0 V Power Supply
• Three-State TTL-Outputs
• CMOS Compatible Clock
APPLICATIONS
• Video Digitizing
• Image Scanners
• Personal Computer Video
• Medical Ultrasound
• Multimedia
• Digital Television
GENERAL DESCRIPTION
The SPT1175 is a CMOS two-step A/D converter capable of
digitizing full scale analog input signals into 8-bit digital words
at a sample rate of 20 MSPS.
For most applications, no external sample-and-hold or
video driving amplifiers are required due to the device's
narrow aperture time, wide bandwidth, and low input ca-
pacitance.
The SPT1175 operates from a single +5.0 V power supply
and has an internal voltage reference which eliminates the
need for external reference circuitry. All digital inputs are
CMOS compatible and the tri-state outputs are TTL-compat-
ible. The SPT1175 is ideal for most video and image pro-
cessing applications that require low power dissipation and
low cost. The SPT1175 is available in 24-lead plastic SOIC,
plastic DIP, and PLCC packages over the commercial tem-
perature range (0 to +70 °C). It is also available in die form.
BLOCK DIAGRAM
VRB
VRBS
Coarse
Sampling
Amplifier
Latch
Reference Matrix
VIN
Fine
Sampling
Amplifier
Fine
Sampling
Amplifier
Analog
Mux
Latch
DVDD
DGND
Encoder
Error
Correction
Circuit
Encoder
Data
Latches
and
3-State
Output
Buffer
OE
DØ (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
Timing
Generator
CLK
VRT
VRTS
AGND AVD
DVDD AGND
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370
1 page  
TYPICAL INTERFACE CIRCUIT
The SPT1175 is an 8-bit analog-to-digital converter which
uses a two-step, ping-pong architecture to perform conver-
sions up to 20 MSPS. Figure 2 shows the typical interface
requirements when using the SPT1175 in normal operation.
The following sections describe the function and operation of
the device.
POWER SUPPLIES AND GROUNDING
The SPT1175 operates from a single +5 V power supply.
AVDD and DVDD must be supplied from the same source
(analog +5 V) to prevent a latch-up condition due to power
supply sequencing. Each power supply pin should be by-
passed as closely as possible to the device. For optimal
performance, both the AGND and DGND should be con-
nected to the system's analog ground plane.
ANALOG INPUT AND VOLTAGE REFERENCE
The SPT1175 input voltage range is VRT>VIN>VRB. Two
reference voltages (VRT and VRB) are required for device
operation. These voltages may be generated externally or
the SPT1175's internal reference may be used.
Inside the SPT1175, reference resistors are placed between
AVDD and VRTS and between AGND and VRBS so that VRTS
and VRBS generate the 2.6 V and 0.6 V references respec-
tively. (See figure 3.) In order to utilize the internal self-bias
reference voltage, VRTS is to be shorted with VRT and the
Figure 2 - Typical Interface Circuit
VRBS pin is to be shorted to the VRB pin. The self-bias internal
reference is not as stable over temperature and supply
variations as externally generated reference voltages but will
perform well in many commercial video applications.
Figure 3 - Reference Circuit Diagram
AVDD
5.0V
SPT1175
AGND
0V
2.6 V 0.6 V
DIGITAL INPUTS AND OUTPUTS
The analog input is sampled and tracked on the first 'H' cycle
of the external clock and is held from the falling edge of CLK.
The output remains valid (output hold time), and the new data
becomes valid (output delay time) after the rising edge of
CLK, delayed by 2.5 clock cycles. The clock input and output
enable input must be driven at CMOS-compatible levels.
EVALUATION BOARD
The EB1175 evaluation board is available to aid designers in
demonstrating the full performance of the SPT1175. This
board includes a reference circuit, clock driver circuit, output
data latches, and an on-board reconstruction DAC. An appli-
cation note describing the operation of the board is available.
Contact the factory for price and delivery.
10
10
10 +
+
10 +
+
+5
R1
2k Q1
+5 V
FB
750 R9
-15 +15
C28
U1=Eleantec, EL2030
U2=OP.07
D1=D2=RCA, SK9091
Q1=Q2=2N2222A
FR=FairRite, 2743001111
All capacitors are 0.01 µF unless
otherwise specified.
VIN
C29
+
4
3
75
R35
2 _U1
7
R37
750 750
R36
+5 V
D1
D2
10 k
R6
_
2 U2
3+
6 R15
10
C58 C59
C8
R10
7.5 k
C60
C61
R8
Q2
-5 2k
750
+5 R2
13 DVDD
14 AVDD
15 AVDD
16 VRTS
17 VRT
18 AVDD
19 VIN
20 AGND
21 AGND
22 VRBS
23 VRB
24 DGND
R13
200
CLK 12
DVDD 11
D7 10(MSB)
D6 9
D5 8
D4 7
D3 6
Outputs
D2 5
D1 4
D0 3 (LSB)
DGND 2
OE 1
EN
3-ST
+5
NOTE: AVDD and DVDD must be supplied from the same source (Analog +5 V)
to prevent a latch-up condition due to power supply sequencing.
SPT
5
SPT1175
6/24/97
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet SPT175.PDF ] | |
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