|
|
PDF ICS9248-146 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-146 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS9248-146 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
Integrated
Circuit
Systems, Inc.
ICS9248-146
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
Single chip clock solution for SIS630S chipsets.
Output Features:
• 3- CPUs @ 2.5V
• 13 - SDRAM @ 3.3V
• 6- PCI @3.3V,
• 2 - AGP @ 3.3V
• 1- 48MHz, @3.3V fixed.
• 1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
• 2- REF @3.3V, 14.318MHz.
Features:
• Up to 166MHz frequency support
• Support FS0-FS3 trapping status bit for I2C read back.
• Support power management: CPU, PCI, SDRAM stops
and Power down Mode form I2C programming.
• Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
• Uses external 14.318MHz crystal
Skew Specifications:
• CPU - CPU: < 175ps
• SDRAM - SDRAM < 250ps (except SDRAM12)
• PCI - PCI: < 500ps
• CPU (early) - PCI: 1-4ns (typ. 2ns)
Pin Configuration
VDDA
1*(AGPSEL)REF0
1*(FS3)REF1
GND
X1
X2
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
VDDAGP
AGPCLK0
AGPCLK1
GND
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDL
47 CPUCLK0
46 CPUCLK1
45 CPUCLK2
44 GND
43 VDDSDR
42 SDRAM0
41 SDRAM1
40 SDRAM2
39 GND
38 SDRAM3
37 SDRAM4
36 SDRAM5
35 VDDSDR
34 SDRAM6
33 SDRAM7
32 GND
31 SDRAM8/PD#
30 SDRAM9/SDRAM_STOP#
29 GND
28 SDRAM10/PCI_STOP#
27 SDRAM11/CPU_STOP#
26 SDRAM12
25 VDDSDR
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
AGP_SEL
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
Stop
SDRAM
DIVDER
Stop
PCI
DIVDER
Stop
AGP
DIVDER
Functionality
48MHz
24_48MHz
REF(1:0)
2
3 CPUCLK (2:0)
SDRAM (12:0)
13
5 PCICLK (4:0)
PCICLK_F
AGP (1:0)
2
FS3 FS2 FS1 FS0
CPU
SDRAM
PCICLK
AGP SEL
=0
AGP SEL
=1
0 0 0 0 66.67 66.67 33.33 66.67 50.00
0 0 0 1 100.00 100.00 33.33 66.67 50.00
0 0 1 0 166.67 166.67 33.33 66.66 55.56
0 0 1 1 133.33 133.33 33.33
0 1 0 0 66.67 100.00 33.33
0 1 0 1 100.00 66.67 33.33
0 1 1 0 100.00 133.33 33.33
0 1 1 1 133.33 100.00 33.33
1 0 0 0 112.00 112.00 33.60
1 0 0 1 124.00 124.00 31.00
66.67
66.67
66.67
66.67
66.67
67.20
62.00
50.00
50.00
50.00
50.00
50.00
56.00
46.50
1 0 1 0 138.00 138.00 34.50 69.00 51.75
1 0 1 1 150.00 150.00 30.00 60.00 50.00
1 1 0 0 66.67 133.33 33.33
1 1 0 1 100.00 150.00 30.00
1 1 1 0 150.00 100.00 30.00
1 1 1 1 160.00 120.00 30.00
66.67
60.00
60.00
60.00
50.00
50.00
50.00
48.00
9248-146 RevA- 4/23/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9248-146
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 2,3 0 REF strength 0=1X, 1=2X
Bit6 45
CPUCLK2 - Stop - Control
0 0=CPU_STOP# will control CPUCLK2,
1=CPUCLK2 is free running even if CPU_STOP# is low
Bit5 -
X AGPSEL (Readback)
Bit4 -
X MODE (Readback)
Bit3 -
X CPU_STOP# (Readback)
Bit2 -
X PCI_STOP# (Readback)
Bit1 -
X SDRAM_STOP# (Readback)
Bit0 -
AGP Speed Toggle
0 0=AGPSEL (pin2) will be determined by latch input setting,
1=AGPSEL will be opposite of latch input setting
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
0 Reserved
0 Reserved
1 Reserved
0 Reserved
1 Reserved
0 Reserved
0 Reserved
1 Reserved
Third party brands and names are the property of their respective owners.
5
5 Page 
ICS9248-146
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248-
146 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
Programming
Header
Via to Gnd
Via to
VDD
2K W
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS9248-146.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS9248-141 | Frequency Generator & Integrated Buffers | Integrated Circuit Systems |
| ICS9248-143 | Frequency Generator & Integrated Buffers | Integrated Circuit Systems |
| ICS9248-146 | Frequency Generator & Integrated Buffers | Integrated Circuit Systems |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |