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PDF ICS9248-150 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-150 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9248-150
Frequency Generator for Multi - Processor Servers
Recommended Application:
ServerWorks Grand Champion Systems.
Output Features:
• 8 - Differential CPU Clock Pairs @ 3.3V
• 1 - 3V 33MHz PCI clocks
• 1 - 48MHz clock
• 1 - Inverted 48MHz clock
• 1 - 14.318 reference output
Features:
• Up to 200MHz frequency support
• Support power management: Power Down Mode
• Supports Spread Spectrum modulation: 0 to -0.5% down
spread.
• Uses external 14.318MHz crystal
• Select logic for Differential Swing Control, Test mode,
Tristate, Power down, Spread Spectrum.
• External resistor for current reference
• FS pins for frequency select
Key Specifications:
• PCI Output jitter <500ps
• CPU Output jitter <200ps
• 48MHz Output jitter <350ps
• REF Output jitter < 1000ps
Pin Configuration
PCICLK
VDD48
FS0/48MHz
FS1/48MHz#
GND48
VDDCPU
CPUCLKT0
CPUCLKC0
GNDCPU
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT2
CPUCLKC2
GNDCPU
CPUCLKT3
CPUCLKC3
VDDCPU
REF
SPREAD#
GNDREF
X1
X2
VDDREF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 SEL100/133
47 GNDPCI
46 VDDA
45 GNDA
44 PD#
43 VDDCPU
42 CPUCLKT4
41 CPUCLKC4
40 GNDCPU
39 CPUCLKT5
38 CPUCLKC5
37 VDDCPU
36 CPUCLKT6
35 CPUCLKC6
34 GNDCPU
33 CPUCLKT7
32 CPUCLKC7
31 VDDCPU
30 MULTSEL0
29 MULTSEL1
28 GND
27 GNDI REF
26 I REF
25 VDDI REF
48-Pin SSOP and TSSOP
Functionality
SEL133/
100
FS0
FS1
Function
0 0 0 Active 100MHz
0 0 1 100MHz Test Mode
0 1 0 100MHz Test Mode
0 1 1 Tristate all outputs
1 0 0 Active 133MHz
1 0 1 133MHz Test Mode
1 1 0 Active 200MHz
1 1 1 Reserved
Analog Power Groups
VDD48, GND48 = 48MHz, PLL2
VDDA=VDD (core supply voltage 3.3V)
GNDA=Ground for core supply
Digital Power Group
VDDREF, GNDREF = REF, Xtal
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
PD#
SPREAD#
MULTSEL(1:0)
SEL100/133
FS(1:0)
Control
Logic
Config.
Reg.
CPU
DIVDER
PCI
DIVDER
48MHz
48MHz#
REF
8 CPUCLKT (7:0)
8 CPUCLKC (7:0)
PCICLK
I REF
9248-150 Rev B 06/12/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data
identified in this publication without further notice. ICS advises
its customers to obtain the latest version of all device data to
verify that any information being relied upon by the customer is
1 page  
ICS9248-150
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating Supply
Current
Powerdown Current
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP
IDD3.3PD
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
2
VSS-0.3
-5
-5
-200
CL = 0 pF; Select @ 100 MHz
CL = 0 pF; Input address to VDD or GND
VDD+0.3
0.8
5
181 250
52 60
Input Frequency
Pin Inductance
Input Capacitance1
Transition time1
Settling time1
Clk Stabilization1
Delay1
Fi
Lpin
CIN
COUT
CINX
Ttrans
Ts
TSTAB
tPZH,tPZL
tPHZ,tPLZ
VDD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
From VDD = 3.3 V to 1% target frequency
Output enable delay (all outputs)
Output disable delay (all outputs)
14.318
7
5
6
27 45
3
3
3
1 10
1 10
1Guaranteed by design, not 100% tested in production.
UNITS
V
V
µA
µA
mA
mA
MHz
nH
pF
pF
pF
ms
ms
ms
ns
ns
Third party brands and names are the property of their respective owners.
5
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet ICS9248-150.PDF ] | |
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