PDF CY7C1480V33 Data sheet ( Hoja de datos )

Número de pieza	CY7C1480V33
Descripción	(CY7C1480V33 / CY7C1482V33 / CY7C1486V33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! PRELIMINARY CY7C1480V33 CY7C1482V33 CY7C1486V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features Functional Description[1] • Supports bus operation up to 250 MHz • Available speed grades are 250, 200,167 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply • 2.5V / 3.3V I/O operation • Fast clock-to-output times — 3.0 ns (for 250-MHz device) — 3.0 ns (for 200-MHz device) — 3.4 ns (for 167-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Single Cycle Chip Deselect • CY7C1480V33 and CY7C1482V33 offered in JEDEC-standard lead-free 100-pin TQFP, 165-Ball fBGA packages. CY7C1486V33 available in 209-Ball BGA packages • IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2,097,152 x 36/4,194,304 x 18,1,048,576 × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 250 MHz 3.0 500 120 200 MHz 3.0 500 120 167 MHz 3.4 450 120 Unit ns mA mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-05283 Rev. C Revised December 3, 2004 1 page Pin Configurations (continued) 12 A NC / 288M A B NC A C DQPC NC D DQC DQC E DQC DQC F DQC DQC G DQC DQC H NC NC J DQD DQD K DQD DQD L DQD DQD M DQD DQD N DQPD NC P NC A R MODE A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 1 A NC / 288M 2 A B NC A C NC NC D NC DQB E NC DQB F NC DQB G NC DQB H NC NC J DQB NC K DQB NC L DQB NC M DQB NC N DQPB NC P NC A R MODE A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A PRELIMINARY CY7C1480V33 CY7C1482V33 CY7C1486V33 165-ball fBGA CY7C1480V33 (2M x 36) 4 567 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO A TMS A0 TCK CY7C1482V33 (4M x 18) 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 11 A NC A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A NC / 144M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A AA 10 11 AA A NC / 144M NC DQPA NC DQA NC DQA NC DQA NC DQA NC ZZ DQA NC DQA NC DQA NC DQA NC NC NC AA AA Document #: 38-05283 Rev. C Page 5 of 30 5 Page Truth Table for Read/Write[4] Function (CY7C1480V33) Read Read Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) Write Bytes B, A Write Byte C – (DQC and DQPC) Write Bytes C, A Write Bytes C, B Write Bytes C, B, A Write Byte D – (DQD and DQPD) Write Bytes D, A Write Bytes D, B Write Bytes D, B, A Write Bytes D, C Write Bytes D, C, A Write Bytes D, C, B Write All Bytes Write All Bytes Truth Table for Read/Write[4] Function (CY7C1482V33) Read Read Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) Write Bytes B, A Write All Bytes Write All Bytes PRELIMINARY CY7C1480V33 CY7C1482V33 CY7C1486V33 GW BWE BWD BWC BWB BWA HHXXXX H L HHHH H L HHH L H L HH L H HLHHL L H L H L HH HLHLHL HLHL LH HLHL L L HL LHHH HL LHHL HL LHLH HL LHL L HL L LHH HL L LHL HL L L LH HL L L L L LXXXXX GW BWE BWB BWA HHXX H L HH HLHL HL LH HL L L HL L L LXXX Document #: 38-05283 Rev. *C Page 11 of 30 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
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