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PDF CY22394 Data sheet ( Hoja de datos )
| Número de pieza | CY22394 | |
| Descripción | Three-PLL Serial-Programmable Flash-Programmable Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY22393/CY223931
CY22394
CY22395
Three-PLL Serial-Programmable
Flash-Programmable Clock Generator
Three-PLL Serial-Programmable Flash-Programmable Clock Generator
Features
Advanced Features
■ Three integrated phase-locked loops (PLLs)
■ Ultra wide divide counters (8-bit Q, 11-bit P, and 7-bit post
divide)
■ Improved linear crystal load capacitors
■ Flash programmability with external programmer
■ Field-programmable
■ Low jitter, high accuracy outputs
■ Power management options (Shutdown, OE, Suspend)
■ Configurable crystal drive strength
■ Frequency select through three external LVTTL inputs
■ 3.3 V operation
■ 16-pin TSSOP package
■ CyClocksRT™ software support
■ Two-wire serial interface for in-system configurability
■ Configurable output buffer
■ Digital VCXO
■ High frequency LVPECL output (CY22394 only)
■ 3.3/2.5 V outputs (CY22395 only)
■ NiPdAu lead finish (CY223931)
Functional Description
The CY22393, CY22394, and CY22395 are a family of parts
designed as upgrades to the existing CY22392 device. These
parts have similar performance to the CY22392, but provide
advanced features to meet the needs of more demanding
applications.
The clock family has three PLLs which, when combined with the
reference, allow up to four independent frequencies to be output
on up to six pins. These three PLLs are completely
programmable.
The CY223931 is the CY22393 with NiPdAu lead finish.
For a complete list of related documentation, click here.
Selector Guide
Part Number Outputs
Input Frequency Range
CY22393_C 6 CMOS
8 MHz–30 MHz (external crystal)
1 MHz–166 MHz (reference clock)
CY22393_I 6 CMOS
8 MHz–30 MHz (external crystal)
1 MHz–166 MHz (reference clock)
CY223931_I 6 CMOS
8 MHz–30 MHz (external crystal)
1 MHz–166 MHz (reference clock)
CY22394_C 1 PECL/
4 CMOS
8 MHz–30 MHz (external crystal)
1 MHz–166 MHz (reference clock)
CY22394_I
1 PECL/
4 CMOS
8 MHz–30 MHz (external crystal)
1 MHz–150 MHz (reference clock)
CY22395_C 4 LVCMOS/ 1 8 MHz–30 MHz (external crystal)
CMOS
1 MHz–166 MHz (reference clock)
CY22395_I
4 LVCMOS/ 1 8 MHz–30 MHz (external crystal)
CMOS
1 MHz–150 MHz (reference clock)
Output Frequency Range
Up to 200 MHz
Up to 166 MHz
Up to 166 MHz
100 MHz–400 MHz (PECL)
Up to 200 MHz (CMOS)
125 MHz–375 MHz (PECL)
Up to 166 MHz (CMOS)
Up to 200 MHz (3.3 V)
Up to 133 MHz (2.5 V)
Up to 166 MHz (3.3 V)
Up to 133 MHz (2.5 V)
Specifics
Commercial temperature
Industrial temperature
Industrial temperature
Commercial temperature
Industrial temperature
Commercial temperature
Industrial temperature
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07186 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 17, 2016
1 page  
CY22393/CY223931
CY22394
CY22395
Pinouts
Figure 1. Pin Diagram: 16-pin TSSOP CY22393/CY223931/CY22394/CY22395
CLKC
VDD
AGND
XTALIN
XTALOUT
XBUF
CLKD
CLKE
1 16
2 CY22393 15
3 CY22393114
4 13
5 12
6 11
7 10
89
SHUTDOWN
/OE
S2/
SUSPEND
CLKC
VDD
AVDD
AGND
SCLK(S1) XTALIN
SDAT(S0) XTALOUT
GND
XBUF
CLKA
CLKB
P-CLK
P+CLK
1 16
2 CY22394 15
3 14
4 13
5 12
6 11
7 10
89
SHUTDOWN
/OE
S2/
SUSPEND
CLKC
VDD
AVDD
AGND
SCLK(S1) XTALIN
SDAT(S0) XTALOUT
GND
CLKA
CLKB
LVDD
LCLKD
LCLKE
1 16
2 CY22395 15
3 14
4 13
5 12
6 11
7 10
89
SHUTDOWN
/OE
S2/
SUSPEND
AVDD
SCLK(S1)
SDAT(S0)
GND/
LGND
LCLKA
LCLKB
Pin Definitions
Name
CLKC
VDD
AGND
XTALIN
XTALOUT
XBUF
LVDD
CLKD or LCLKD
P– CLK
CLKE or LCLKE
P+ CLK
CLKB or LCLKB
CLKA or LCLKA
GND/LGND
SDAT (S0)
SCLK (S1)
AVDD
S2/
SUSPEND
SHUTDOWN/
OE
Pin Number
CY22393
CY223931
1
2
3
4
5
6
N/A
7
N/A
8
N/A
9
10
11
12
13
14
15
16
Pin Number
CY22394
1
2
3
4
5
6
N/A
N/A
7
N/A
8
9
10
11
12
13
14
15
16
Pin Number
CY22395
Description
1 Configurable clock output C
2 Power supply
3 Analog Ground
4 Reference crystal input or external reference clock input
5 Reference crystal feedback
N/A Buffered reference clock output
6 Low voltage clock output power supply
7 Configurable clock output D; LCLKD referenced to LVDD
N/A LV PECL output[1]
8 Configurable clock output E; LCLKE referenced to LVDD
N/A LV PECL output[1]
9 Configurable clock output B; LCLKB referenced to LVDD
10 Configurable clock output A; LCLKA referenced to LVDD
11 Ground
12 Serial port data. S0 value latched during start up
13 Serial port clock. S1 value latched during start up
14 Analog power supply
15
General purpose input for frequency control; bit 2. Optionally,
Suspend mode control input
Places outputs in tristate condition and shuts down chip when
16 LOW. Optionally, only places outputs in tristate condition and
does not shut down chip when LOW
Note
1. LVPECL outputs require an external termination network.
Document Number: 38-07186 Rev. *L
Page 5 of 25
5 Page 
CY22393/CY223931
CY22394
CY22395
Serial Bus Programming Protocol and Timing
The CY22393, CY22394 and CY22395 have a 2-wire serial
interface for in-system programming. They use the SDAT and
SCLK pins, and operate up to 400 kbit/s in Read or Write mode.
Except for the data hold time, it is compliant with the I2C bus
standard. The basic Write serial format is as follows:
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit. The basic serial format is
illustrated in Figure 2 on page 13.
Default Startup Condition for the CY22393/931/94/95
The default (programmed) condition of each device is generally
set by the distributor, who programs the device using a customer
specified JEDEC file produced by CyClocksRT, Cypress’s propri-
etary development software. Parts shipped by the factory are
blank and unprogrammed. In this condition, all bits are set to 0,
all outputs are tristated, and the crystal oscillator circuit is active.
While users can develop their own subroutine to program any or
all of the individual registers as described in the following pages,
it may be easier to simply use CyClocksRT to produce the
required register setting file.
Device Address
The device address is a 7-bit value that is configured during Field
Programming. By programming different device addresses, two
or more parts are connected to the serial interface and can be
independently controlled. The device address is combined with
a read/write bit as the LSB and is sent after each start bit.
The default serial interface address is 69H, but must there be a
conflict with any other devices in your system, this can also be
changed using CyClocksRT.
Data Valid
Data is valid when the clock is HIGH, and can only be
transitioned when the clock is LOW as illustrated in Figure 3 on
page 13.
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in Figure 4 on page 14.
Start Sequence - Start Frame is indicated by SDAT going LOW
when SCLK is HIGH. Every time a start signal is given, the next
8-bit data must be the device address (seven bits) and a R/W bit,
followed by register address (eight bits) and register data (eight
bits).
Stop Sequence - Stop Frame is indicated by SDAT going HIGH
when SCLK is HIGH. A Stop Frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
Acknowledge Pulse
During Write Mode the CY22393, CY22394, and CY22395
respond with an Acknowledge pulse after every eight bits. To do
this, they pull the SDAT line LOW during the N*9th clock cycle,
as illustrated in Figure 5 on page 14. (N = the number of bytes
transmitted). During Read Mode, the master generates the
acknowledge pulse after the data packet is read.
Document Number: 38-07186 Rev. *L
Page 11 of 25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet CY22394.PDF ] | |
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