PDF CY22392 Data sheet ( Hoja de datos )

Número de pieza	CY22392
Descripción	Three-PLL General Purpose Flash Programmable Clock Generator
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY22392 Three-PLL General Purpose Flash Programmable Clock Generator Three-PLL General Purpose Flash Programmable Clock Generator Features ■ Three Integrated Phase-locked Loops ■ Ultra Wide Divide Counters (8-bit Q, 11-bit P, and 7-bit Post Divide) ■ Improved Linear Crystal Load Capacitors ■ Flash Programmability ■ Field Programmable ■ Low-jitter, High-accuracy Outputs ■ Power Management Options (Shutdown, OE, Suspend) ■ Configurable Crystal Drive Strength ■ Frequency Select through three External LVTTL Inputs ■ 3.3 V Operation ■ 16-pin TSSOP and SOIC Packages ■ CyClocksRT™ Support Benefits ■ Generates up to three unique frequencies on six outputs up to 200 MHz from an external source. Functional upgrade for current CY2292 family. ■ Enables 0 ppm frequency generation and frequency conversion under the most demanding applications. Logic Block Diagram XTALIN XTALOUT OSC. ■ Improves frequency accuracy over temperature, age, process, and initial offset. ■ Nonvolatile programming enables easy customization, fast turnaround, performance tweaking, design timing margin testing, inventory control, lower part count, and more secure product supply. In addition, any part in the family can also be programmed multiple times, which reduces programming errors and provides an easy upgrade path for existing designs. ■ In-house programming of samples and prototype quantities is available using the CY3672 development kit. Production quantities are available through Cypress Semiconductor’s value added distribution partners or by using third party programmers from BP Microsystems, HiLo Systems, and others. ■ Performance suitable for high-end multimedia, communications, industrial, A/D Converters, and consumer applications. ■ Supports numerous low power application schemes and reduces EMI by enabling unused outputs to be turned off. ■ Adjusts crystal drive strength for compatibility with virtually all crystals.3-bit external frequency select options for PLL1, CLKA, and CLKB. ■ Industry-standard supply voltage.Industry-standard packaging saves on board space.Easy to use software support for design entry. Functional Description For a complete list of related documentation, click here. XBUF SHUTDOWN/OE S0 S1 S2/SUSPEND CONFIGURATION FLASH PLL1 11 BIT P 8 BIT Q PLL2 11 BIT P 8 BIT Q PLL3 11 BIT P 8 BIT Q 4x4 Crosspoint Switch Divider /2,3, or 4 Divider 7 BIT Divider 7 BIT Divider 7 BIT Divider 7 BIT CLKE CLKD CLKC CLKB CLKA Cypress Semiconductor Corporation • 198 Champion Court Document Number: 38-07013 Rev. L • San Jose, CA 95134-1709 • 408-943-2600 Revised September 28, 2016 1 page CY22392 associated logic, while suspending an output simply forces a tristate condition. Improving Jitter Jitter Optimization Control is useful in mitigating problems related to similar clocks switching at the same moment, causing excess jitter. If one PLL is driving more than one output, the negative phase of the PLL can be selected for one of the outputs (CLKA–CLKD). This prevents the output edges from aligning, enabling superior jitter performance. Power Supply Sequencing For parts with multiple VDD pins, there are no power supply sequencing requirements. The part is not fully operational until all VDD pins have been brought up to the voltages specified in the Operating Conditions. All grounds must be connected to the same ground plane. CyberClocks™ Software The CyberClocks application enables users to configure this device. Within CyberClocks, select the CyClocksRT tool. The easy-to-use interface offers complete control of the many features of this family including input frequency, PLL, output frequencies, and different functional options. Data sheet frequency range limitations are checked and performance tuning is automatically applied. CyClocksRT also has a power estimation feature that enables you to see the power consumption of your specific configuration. Download a copy of CyberClocks free on Cypress’s web site at www.cypress.com. Install and run it on any PC running Windows. Device Programming Part numbers starting with CY22392F are ‘field programmable’ devices. Field programmable devices are shipped unprogrammed, and must be programmed prior to installation on a PCB. After a programming file (.jed) is created using CyberClocks software, devices can be programmed in small quantities using the CY3672 programmer and CY3698 [1] adapter. Volume programming is available through Cypress Semiconductor’s value added distribution partners or by using third party programmers from BP Microsystems, HiLo Systems, and others. For sufficiently large volumes, Cypress can supply pre-programmed devices with a part number extension that is configuration-specific. Junction Temperature Limitations It is possible to program the CY22392 such that the maximum junction temperature rating is exceeded. The package JA is 115 C/W. Use the CyClocksRT power estimation feature to verify that the programmed configuration meets the junction temperature and package power dissipation maximum ratings. Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Supply Voltage .............................................–0.5 V to +7.0 V DC Input Voltage ........................ –0.5 V to + (AVDD + 0.5 V) Storage Temperature ............................... –65 C to +125 C Junction Temperature ................................................ 125 C Data Retention at Tj = 125 C ..............................> 10 years Maximum Programming Cycles .......................................100 Package Power Dissipation ..................................... 350 mW Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. 2000 V Latch up (according to JEDEC 17) ..................... > ±200 mA Operating Conditions The following table lists the recommended operating conditions. [2] Parameter Description Min Typ Max Unit VDD/AVDD TA Supply Voltage Commercial Operating Temperature, Ambient Industrial Operating Temperature, Ambient 3.135 3.3 3.465 V 0 – +70 C –40 – +85 C CLOAD_OUT fREF Maximum Load Capacitance External Reference Crystal External Reference Clock [3], Commercial – – 15 pF 8 – 30 MHz 1 – 166 MHz External Reference Clock [3], Industrial 1 – 150 MHz tPU Power up time for all VDD’s to reach minimum specified voltage (power 0.05 – 500 ms ramps must be monotonic) Notes 1. Programming of only 16-pin TSSOP package is supported by CY3698. For programming support of 16-pin SOIC package, contact your local FAE. 2. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions. 3. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. Document Number: 38-07013 Rev. L Page 5 of 14 5 Page Acronyms Acronym Description CMOS Complementary Metal Oxide Semiconductor EMI Electromagnetic Interference FET Field-Effect Transistor FTG Frequency Timing Generator JEDEC Joint Electron Devices Engineering Council LVTTL Low Voltage Transistor-Transistor Logic OSC Oscillator PCB Printed Circuit Board PLL Phase Locked Loop TSSOP Thin Shrink Small Outline Package CY22392 Document Conventions Units of Measure Symbol °C MHz  F mA mm ms mW ns % pF ppm ps V W Unit of Measure degree Celsius megahertz microampere microfarad milliampere millimeter millisecond milliwatt nanosecond percent picofarad parts per million picosecond volt watt Document Number: 38-07013 Rev. *L Page 11 of 14 11 Page

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