PDF SPT7861 Data sheet ( Hoja de datos )

Número de pieza	SPT7861
Descripción	10-BIT / 40 MSPS / 160 mW A/D CONVERTER
Fabricantes	Fairchild Semiconductor
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No Preview Available ! SPT7861 10-BIT, 40 MSPS, 160 mW A/D CONVERTER FEATURES • Monolithic 40 MSPS converter • 160 mW power dissipation • On-chip track-and-hold • Single +5 V power supply • TTL/CMOS outputs • 5 pF input capacitance • Low cost • Tri-state output buffers • High ESD protection: 3,500 V minimum • Selectable +3 V or +5 V logic I/O TECHNICAL DATA JUNE 25, 2001 APPLICATIONS • All high-speed applications where low power dissipation is required • Video imaging • Medical imaging • Radar receivers • IR imaging • Digital communications GENERAL DESCRIPTION The SPT7861 is a 10-bit monolithic, low-cost, ultralow- power analog-to-digital converter capable of minimum word rates of 40 MSPS. This is a pin-compatible improved version of the SPT7860. The on-chip track-and-hold func- tion assures excellent dynamic performance without the need for external components. The input drive require- ments are minimized due to the SPT7861’s low input capacitance of only 5 pF. Power dissipation is extremely low at only 160 mW typical at 40 MSPS with a power supply of +5.0 V. The digital out- puts are +3 V or +5 V, and are user selectable. The SPT7861 is pin-compatible with an entire family of 10-bit, CMOS converters (SPT7835/40/50/55/60/61), which sim- plifies upgrades. The SPT7861 has incorporated propri- etary circuit design and CMOS processing technologies to achieve its advanced performance. Inputs and outputs are TTL/CMOS-compatible to interface with TTL/CMOS logic systems. Output data format is straight binary. The SPT7861 is available in 28-lead SOIC and 32-lead small (7 mm square) TQFP packages over the commer- cial temperature range. BLOCK DIAGRAM AIN 1:16 Mux ADC Section 1 T/H Auto- Zero CMP CLK In Enable Data Valid P1 ...P2 Timing and P15 Control P16 ...ADC Section 2 ADC Section 15 ADC Section 16 T/H Auto- Zero CMP 11-Bit SAR 11 DAC ... 11-Bit SAR 11 DAC Ref In Reference Ladder VREF 11 ... 11 11 11 11-Bit 16:1 Mux/ Error Correction D10 Overrange D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) 1 page Figure 1A – Timing Diagram 1 1 ANALOG IN CLOCK IN 3 5 9 7 SAMPLING CLOCK (Internal) DATA OUTPUT DATA VALID INVALID 11 13 17 15 VALID 1 2 3 45 Figure 1B – Timing Diagram 2 CLOCK IN tCLK tC tCH tCL DATA Data 0 OUTPUT Data 1 DATA VALID tOD tS tS tCH Data 2 tCL Data 3 Table I – Timing Parameters DESCRIPTION PARAMETERS MIN TYP MAX UNITS Conversion Time tC tCLK ns Clock Period tCLK 25 ns Clock High Duty Cycle tCH 40 50 60 % Clock Low Duty Cycle tCL 40 50 60 % Clock to Output Delay (15 pF Load) tOD 17 ns Clock to DAV tS 10 ns SPT7861 5 6/25/01 5 Page PIN ASSIGNMENTS AGND 1 VRHF 2 VRHS 3 N/C 4 VRLS 5 VRLF 6 VIN 7 AGND 8 VCAL 9 AVDD 10 DVDD 11 DGND 12 CLK 13 DAV 14 SOIC 28 D10 27 D9 26 D8 25 D7 24 D6 23 D5 22 OVDD 21 OGND 20 D4 19 D3 18 D2 17 D1 16 D0 15 EN VRLF VIN AGND AGND VCAL AVDD AVDD DVDD 1 2 3 4 5 6 7 8 TQFP 24 D7 23 D6 22 D5 21 OVDD 20 OGND 19 D4 18 D3 17 D2 PIN FUNCTIONS Name AGND VRHF VRHS VRLS VRLF VCAL VIN AVDD DVDD DGND CLK EN D0–9 D10 DAV OVDD OGND N/C Function Analog Ground Reference High Force Reference High Sense Reference Low Sense Reference Low Force Calibration Reference Analog Input Analog VDD Digital VDD Digital Ground Input Clock ƒCLK = FS (TTL) Output Enable Tri-State Data Output, (D0=LSB) Tri-State Output Overrange Data Valid Output Digital Output Supply Digital Output Ground No Connect ORDERING INFORMATION PART NUMBER SPT7861SCS SPT7861SCT TEMPERATURE RANGE 0 to +70 °C 0 to +70 °C PACKAGE TYPE 28L SOIC 32L TQFP DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com © Copyright 2002 Fairchild Semiconductor Corporation SPT7861 11 6/25/01 11 Page

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