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PDF SPT7721 Data sheet ( Hoja de datos )
| Número de pieza | SPT7721 | |
| Descripción | 8-BIT / 250 MSPS ADC WITH DEMUXED OUTPUTS | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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SPT7721
8-BIT, 250 MSPS ADC WITH DEMUXED OUTPUTS
FEATURES
• TTL/CMOS/PECL compatible
• High conversion rate: 250 MSPS
• Single +5 V power supply
• Very low power dissipation: 310 mW
• Power-down mode
• +3.0 V/+5.0 V (LVCMOS) digital output logic
compatibility
• Demuxed output ports
TECHNICAL DATA
NOVEMBER 8, 2001
APPLICATIONS
• RGB video processing
• Digital communications
• High-speed instrumentation
• Projection display systems
GENERAL DESCRIPTION
The SPT7721 is a high-speed, 8-bit analog-to-digital con-
verter implemented in an advanced BiCMOS process. An
advanced folding and interpolating architecture provides
both a high conversion rate and very low power dissipation
of only 310 mW. The analog inputs can be operated in
either single-ended or differential input mode. A 2.5 V com-
mon mode reference is provided on chip for the single-
ended input mode to minimize external components.
The SPT7721 digital outputs are demuxed (double-wide)
with both dual-channel and single-channel selectable out-
put modes. Demuxed mode supports either parallel
aligned or interleaved data output. The output logic is both
+3.0 V and +5.0 V compatible. The SPT7721 is available in
a 44-lead TQFP surface mount package over the industrial
temperature range of –40 to +85 °C.
BLOCK DIAGRAM AGND DGND
AVCC
OVDD
VIN+ 8-Bit
250 MSPS
VIN ADC
CLK CLK
Common Mode
Voltage
Reference
Data Output
Mode Control
+2.5 V
VCM
22
PD CLK CLK Reset DMODE1,2
&
Reset
DA0DA7
DB0DB7
DCLKOUT
DCLKOUT
1 page  
TYPICAL PERFORMANCE CHARACTERISTICS
Input Bandwidth
1
0
1
2
3
4
5
0
100 200 300 400 500 600
Input Frequency (MHz)
Common-Mode Reference Voltage vs VCC
2.50
2.49
2.48
2.47
2.46
2.45
2.44
2.43
2.42
2.41
2.40
4.5 4.7 4.9 5.1 5.3 5.5
VCC V
5.7
OVDD Current vs Clock Frequency, Dual Mode
120
100
80
Output VDD=5 V
60
Output VDD=3 V
40
20
0
0 50 100 150 200 250 300
Clock Frequency (MHz)
Total Power vs Clock Frequency
with 6 pF loads
1000
800
OVDD=5 V
700
OVDD Current vs Clock Frequency, Single Mode
60
Output VDD=5 V
50
40
30 Output VDD=3 V
20
10
0
0 25 50 75 100 125 150
Clock Frequency (MHz)
Differential Input Common-Mode Operating Range
400 mVP-P
6
5
4
600
500
400
300
0
OVDD=3 V
50 100 150 200 250
Clock Frequency (MHz)
300
3
Common-Mode Operating Range
2
1
0
50 40
20
0 20 40 60
Temperature (°C)
80
100
SPT7721
5 11/8/01
5 Page 
PIN ASSIGNMENTS
AGND
PD
CLK
CLK
RESET
RESET
OVDD
DGND
DA7 (MSB)
DA6
DA5
1
2
3
4
5
6
7
8
9
10
11
SPT7721
TOP VIEW
44L TQFP
33 AGND
32 DMODE1
31 DMODE2
30 OVDD
29 DGND
28 DCLKOUT
27 DCLKOUT
26 DB7 (MSB)
25 DB6
24 DB5
23 DB4
PIN FUNCTIONS
Pin Name
VIN+
VIN–
DA0–DA7
Description
Non-Inverted Analog Input; nominally 1 VP-P;
100k pullup to VCC and 100k pulldown to AGND,
internally
Inverted Analog Input; nominally 1 VP-P; 100k
pullup to VCC and 100k pulldown to AGND,
internally
Data output; Bank A. 3 V / 5 V LVCMOS
compatible.
DB0–DB7
DCLKOUT
DCLKOUT
CLK
CLK
RESET
RESET
DMODE1,2
PD
VCM
AVCC
OVDD
AGND
DGND
Data output; Bank B. 3 V / 5 V LVCMOS
compatible.
Non-Inverted data output clock. 3 V / 5 V
LVCMOS compatible.
Inverted data output clock. 3 V / 5 V LVCMOS
compatible.
Non-Inverted clock input pin; 100k pulldown to
AGND, internally
Inverted clock input pin; 17.5k pullup to VCC and
7.5k pulldown to AGND, internally
RESET synchronizes the data sampling and data
output bank relationship when in Dual Channel
Mode (DMODE1 = 0); 100k pulldown to AGND,
internally
Inverted RESET input pin; 17.5k pullup to VCC
and 7.5k pulldown to AGND, internally
Internally:
100k pulldown to AGND on DMODE1
50k pullup to VCC on DMODE2
Data Output Mode pins:
DMODE1 = 0, DMODE2 = 0: Parallel Dual
Channel Output
DMODE1 = 0, DMODE2 = 1: Interleaved Dual
Channel Output
DMODE1 = 1, DMODE2 = X: Single Channel
Data Output on Bank A (125 MSPS max)
Power Down pin; PD = 1 for power-down mode.
Outputs set to high impedance in power-down
mode; 100k pulldown to AGND, internally
2.5 V Common Mode Voltage Reference Output
+5 V Analog Supply
+3 V / +5 V Digital Output Supply
Analog Ground
Digital Ground
ORDERING INFORMATION
PART NUMBER
SPT7721SIT
TEMPERATURE RANGE
–40 to +85 °C
PACKAGE
44L TQFP
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR
USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR
THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
www.fairchildsemi.com
© Copyright 2002 Fairchild Semiconductor Corporation
SPT7721
11 11/8/01
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet SPT7721.PDF ] | |
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