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PDF CS18LV10245 Data sheet ( Hoja de datos )
| Número de pieza | CS18LV10245 | |
| Descripción | HIgh Speed Super Low Power SRAM | |
| Fabricantes | CHIPLUS | |
| Logotipo |  |
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High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
DESCRIPTION
The CS18LV10245 is a high performance, high speed and super low power CMOS Static
Random Access Memory organized as 131,072 words by 8bits and operates from a wide range of
4.5 to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high
speed, super low power features and maximum access time of 55/70ns in 5V operation. Easy
memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable
(/OE).
The CS18LV10245 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS18LV10245 is available in JEDEC standard 32-pin
sTSOP - I (8x13.4 mm), TSOP - I (8x20mm), SOP (450 mil) and PDIP (600 mil) packages.
FEATURES
1. Fully static operation and Tri-state output
2. TTL compatible inputs and outputs
3. Ultra low power consumption :
z 2.0V (min) data retention
z Low operation voltage : 4.5 ~ 5.5V ; 5mA＠1MHz (Max.) operating current (Vcc = 5.0V)
4. Standby Typ. = 0.50uA, (Typical value @ Vcc = 5.0V, TA = 25 0C)
5. Standard pin configuration
z 32 - SOP 450mil
z 32 - sTSOP-I - 8X13.4mm
z 32 - TSOP-I 8X20mm
z 32 - PDIP 600mil
Product Family
Part No.
Operating Temp Vcc. Range Speed (ns) Standby (Typ.) Package Type
CS18LV10245CC
32 SOP
CS18LV10245DC
CS18LV10245EC
0~70oC
0.50uA
32 STSOP
32 TSOP (I)
CS18LV10245LC
CS18LV10245CI
4.5 ~ 5.5
55/70
32 PDIP
32 SOP
CS18LV10245DI
CS18LV10245EI
-40~85oC
0.80uA
32 STSOP
32 TSOP (I)
CS18LV10245LI
32 PDIP
Note: Green package part no, sees order information.
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P1
1 page  
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
Parameter
Name
Parameter
Test Conduction
MIN TYP(1) MAX Unit
VIL Guaranteed Input Low
Voltage (2)
-0.5 0.8 V
VIH Guaranteed Input High
Voltage (2)
2.0 Vcc+0.2 V
IIL Input Leakage Current VCC=MAX, VIN=0 to VCC
IOL Output Leakage
VCC=MAX, /CE=VIN, or
Current
/OE=VIN , VIO=0V to VCC
1 uA
1 uA
VOL
Output Low Voltage VCC=MAX, IOL = 2mA
0.4 V
VOH
ICC
Output High Voltage
Operating Power
Supply Current
VCC=MIN, IOH = -1mA
/CE=VIL, IDQ=0mA, F=FMAX(3)
2.4
V
35 mA
ICCSB Standby Supply - TTL /CE=VIH, IDQ=0mA,
ICCSB1 Standby Current
/CE≧VCC-0.2V, VIN≧
-CMOS
VCC-0.2V or VIN≦0.2V
1. Typical characteristics are at TA = 25oC.
2 mA
0.3 10 uA
2. These are absolute values with respect to device ground and all overshoots due to system or tester
notice are included.
3. Fmax = 1/tRC.
DATA RETENTION CHARACTERISTICS ( TA = 0 to +70oC )
Parameter
Name
Parameter
Test Conduction
MIN TYP(1) MAX
VRD
VCC for Data Retention
/CE≧VCC-0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
1.5
ICCDR
Data Retention Current
/CE≧VCC-0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
0.2 2.0
TCDR
Chip Deselect to Data
Retention Time
See Retention Waveform
0
tR Operation Recovery Time
1. Vcc = 3.0V, TA = + 25oC. 2. tRC= Read Cycle Time.
tRC (2)
Unit
V
uA
ns
ns
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P5
5 Page 
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
NOTES:
1. TAS is measured from the address valid to the beginning of write.
2. The internal write time of the memory is defined by the overlap of /CE and /WE low. All
signals must be active to initiate a write and any one signal can terminate a write by
going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
3. TWR is measured from the earlier of /CE or /WE going high or CE2 going low at the end
of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the /CE low transition occurs simultaneously with the /WE low transitions or after the
/WE transition, output remain in a high impedance state.
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P 11
11 Page | ||
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