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PDF DSM2180F3 Data sheet ( Hoja de datos )
| Número de pieza | DSM2180F3 | |
| Descripción | DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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DSM2180F3
DSM (Digital Signal Processor System Memory)
For Analog Devices ADSP-218X Family (5V Supply)
FEATURES SUMMARY
s Glueless Connection to DSP
– Easily add memory, logic, and I/O to DSP
s 128K Byte Flash Memory
– For Bootloading and/or Data Overlay Memory
– Programmable Decoding and Paging Logic
allows accessing Flash memory as Byte DMA
(BDMA) and as External Data Overlay mem-
ory
– Rapidly access Flash memory with BDMA for
booting and loading internal DSP Overlay
memory. Alternatively access the same Flash
memory as External Data Overlay memory to
efficiently write Flash memory with code up-
dates and data, a byte at a time with no DMA
setup overhead
– Individual 16K Byte Flash memory sectors
match size of DSP External Data Overlay
window for efficient data management. Inte-
grated page logic provides easy DSP access
to all 128K Bytes.
– DSM connects to lower byte of 16-bit DSP
data bus. Byte-wide accesses to 8-bit BDMA
space. Half-word accesses to 16-bit Data
Memory Overlay and 16-bit I/O Mem space.
s 5V Devices (±10%)
s Up to 16 Multifunction I/O Pins
– Increase total DSP system I/O capability
– I/O controlled by DSP software or PLD logic
– 8mA I/O pin drive at 5 Vcc
s General purpose PLD
– Over 3,000 Gates of PLD with 16 macro cells
– Use for peripheral glue logic to keypads, con-
trol panel, displays, LCD, UART devices, etc.
– Eliminate PLDs and external logic devices
– Create state machines, chip selects, simple
shifters and counters, clock dividers, delays
– Simple PSDsoft ExpressTM software ...Free
Figure 1. Packages
PQFP52 (T)
PLCC52 (K)
s In-System Programming (ISP) with JTAG
– Program entire chip in 10-20 seconds with no
involvement of the DSP
– Eliminate sockets for pre-programmed mem-
ory and logic devices
– Efficient manufacturing allows easy product
testing and Just-In-Time inventory
– Use low-cost FlashLINKTM cable with PC
s Content Security
– Programmable Security Bit blocks access of
device programmers and readers
s Zero-Power Technology
– 75 µA standby at VCC=5V
s Small Packaging
– 52-pin PQFP or 52-pin PLCC
s Memory Speed
– 90 ns
December 2001
1/63
1 page  
Figure 4. System Block Diagram, Two-Chip Solution
DSM2180F3
The two-chip combination of a DSP and a DSM
device is ideal for systems which have limitations
on size, EMI levels, and power consumption. DSM
memory and logic are “zero-power”, meaning they
automatically go to standby between memory ac-
cesses or logic input changes, producing low ac-
tive and standby current consumption, which is
ideal for battery powered products.
5/63
5 Page 
DSM2180F3
TYPICAL CONNECTIONS
Figure 6 shows a typical connection scheme.
Many connection possibilities exist since most
DSM pins are multipurpose. The scheme illustrat-
ed is ideal for a design that needs fast JTAG ISP,
Eight additional general I/O with PLD capability,
access to Flash memory as Byte DMA or as Data
Overlay memory, and the DSP uses Power Down
mode. If your design needs more I/O, or Byte DMA
access to Flash memory is all that is needed (no
Data Overlay), or lowest power consumption is not
an issue, then consider the following options.
Port C JTAG: Figure 6 shows all six JTAG sig-
nals in use full time (not multiplexed with I/0). Us-
ing six-pin JTAG can reduce ISP time by as much
as 30% compared to four-pin JTAG. Alternatively,
four-pin JTAG (TMS, TCK, TDI, TDO) can be used
if more general I/O pins are needed and the few
extra seconds of programming time is not crucial,
freeing up pins PC3 and PC4. Other JTAG options
include mutiplexing JTAG pins with general I/O
(see “Programming In-Circuit using JTAG ISP” on
page 41 and Application Note AN1153) or not us-
ing JTAG at all. If no JTAG is used, the DSM de-
vice has to be programmed on a conventional
programmer before it is installed on the circuit
board. Using no JTAG makes more I/O available.
Pin PD1. If Flash memory will be accessed only
using Byte DMA mode in your design, and no ex-
ternal Data Overlay memory accesses are used,
then pin PD1 can be used for other purposes
(MCUI/O, common CPLD clock input, external
chip select, or PLD input)
Pin PD2. If the DSP will not use Power Down
mode, then PD2 can be used for other purposes
(MCUI/O, external chip select, PLD input)
Pins PC2 and PC7. In Figure 6, these two pins
are used as dedicated address inputs connected
to DSP address outputs. This will route DSP ad-
dress signals A16 and A17 directly into the DPLD.
Be aware that any free pin on Port B, Port C, or
Port D may be used for DSP address inputs, it
does not have to be pins PC2 and PC7.
Pin PB0. This pin is shown as a chip select for an
external peripheral device such as a 16450 or
16550 UART. Equivalently, any free pin on Ports
B, C, or D may be used for this.
11/63
11 Page | ||
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| PDF Descargar | [ Datasheet DSM2180F3.PDF ] | |
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