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PDF CY62137CV18 Data sheet ( Hoja de datos )
| Número de pieza | CY62137CV18 | |
| Descripción | 128K x 16 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62137CV18 MoBL2™
Features
• High Speed
— 55 ns and 70 ns availability
• Low voltage range:
— CY62137CV18: 1.65V−1.95V
• Pin Compatible w/ CY62137V18/BV18
• Ultra-low active power
— Typical Active Current: 0.5 mA @ f = 1 MHz
— Typical Active Current: 1.5 mA @ f = fmax (70 ns
speed)
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62137CV18 is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6 128K x 16
A5 RAM Array
A4 2048 X 1024
A3
A2
A1
A0
128K x 16 Static RAM
power consumption by 99% when addresses are not toggling.
The device can also be put into standby mode when deselect-
ed (CE HIGH or both BLE and BHE are HIGH). The input/out-
put pins (I/O0 through I/O15) are placed in a high-impedance
state when: deselected (CE HIGH), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are dis-
abled (BHE, BLE HIGH), or during a write operation (CE LOW,
and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O8 to I/O15. See the
Truth Table at the back of this data sheet for a complete de-
scription of read and write modes.
The CY62137CV18 is available in a 48-ball FBGA package.
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power -Down
Circuit
CE
BHE
BLE
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation.
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05017 Rev. *B
Revised October 31, 2001
1 page  
CY62137CV18 MoBL2™
Switching Characteristics Over the Operating Range[8]
55 ns
70 ns
Parameter
Description
Min. Max. Min.
Max.
Unit
READ CYCLE
tRC Read Cycle Time
55
70
tAA Address to Data Valid
55
tOHA
Data Hold from Address Change
10
10
tACE CE LOW to Data Valid
55
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[9]
OE HIGH to High Z[9, 10]
CE LOW to Low Z[9]
CE HIGH to High Z[9, 10]
25
55
20
5 10
20
tPU CE LOW to Power-Up
0
0
tPD CE HIGH to Power-Down
55
tDBE
BLE/BHE LOW to Data Valid
55
tLZBE
BLE/BHE LOW to Low Z[9]
5
5
tHZBE
BLE/BHE HIGH to High Z[9, 10]
20
WRITE CYCLE[11]
70
70
35
25
25
70
70
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC Write Cycle Time
55
70
ns
tSCE CE LOW to Write End
40
60
ns
tAW
Address Set-Up to Write End
40
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
50
ns
tBW
BLE/BHE LOW to Write End
40
60
ns
tSD Data Set-Up to Write End 25
30
ns
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High Z[9, 10]
WE HIGH to Low Z[9]
00
20 25
5 10
ns
ns
ns
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the
specified IOL/IOH and 30 pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high impedance state.
11. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05017 Rev. *B
Page 5 of 11
5 Page 
CY62137CV18 MoBL2™
Document Title: CY62137CV18 MoBL2™, 128K x 16 Static RAM
Document Number: 38-05017
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
** 106265 5/7/01 HRT/MGN New Data Sheet
*A 108941 08/24/01 MGN From Preliminary to Final
.
*B 110572 11/02/01 MGN Format standardization. Improved Typical Icc @ f = 1 MHz for 55 ns & 70 ns
and Max Icc @ f = fMAX for 70 ns. Improved Typical and Max ICCDR.
Document #: 38-05017 Rev. *B
Page 11 of 11
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