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PDF CY62137CV33 Data sheet ( Hoja de datos )
| Número de pieza | CY62137CV33 | |
| Descripción | (CY62137CV25 / CY62137CV30 / CY62137CV33) 2M (128K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Features
• Very high speed: 55 ns and 70 ns
• Voltage range:
— CY62137CV25: 2.2V–2.7V
— CY62137CV30: 2.7V–3.3V
— CY62137CV33: 3.0V–3.6V
— CY62137CV: 2.7V–3.6V
• Pin-compatible with the CY62137V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 5.5 mA @ f = fmax (70-ns
speed)
• Low and ultra-low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball FBGA
Functional Description[1]
The CY62137CV25/30/33 and CY62137CV are high-perfor-
mance CMOS static RAMs organized as 128K words by 16
bits. These devices feature advanced circuit design to provide
ultra-low active current. This is ideal for providing More Battery
2M (128K x 16) Static RAM
Life™ (MoBL®) in portable applications such as cellular tele-
phones. The devices also has an automatic power-down fea-
ture that significantly reduces power consumption by 80%
when addresses are not toggling. The device can also be put
into standby mode reducing power consumption by more than
99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input/output pins (I/O0 through I/O15) are placed
in a high-impedance state when: deselected (CE HIGH), out-
puts are disabled (OE HIGH), both Byte High Enable and Byte
Low Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Logic Block Diagram
A1010
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
128K x 16
RAM Array
2048 x 1024
I/O0 – I/O7
I/O8 – I/O15
COLUMN DECODER
Power -down
Circuit
CE
BHE
BLE
BHE
WE
CE
OE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05201 Rev. *D
Revised September 20, 2002
1 page  
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
ICCDR
VCC for Data Retention
Data Retention Current
tCDR[6]
tR[7]
Chip Deselect to Data Retention Time
Operation Recovery Time
Conditions
VCC= 1.5V
LL
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
SL
Data Retention Waveform[8]
Min.
1.5
Typ.[5] Max.
Vccmax
16
4
Unit
V
µA
0 ns
tRC ns
VCC
CE or
BHE.BLE
VCC(min.)
tCDR
DATA RETENTION MODE
VDR > 1.5 V
VCC(min.)
tR
Switching Characteristics Over the Operating Range[9]
55 ns
70 ns
Parameter
Description
Min Max Min Max Unit
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE[11]
tHZBE
Write Cycle[13]
Read Cycle Time
55 70 ns
Address to Data Valid
55 70 ns
Data Hold from Address Change
10
10
ns
CE LOW to Data Valid
55 70 ns
OE LOW to Data Valid
OE LOW to Low-Z[10]
OE HIGH to High-Z[10, 12]
CE LOW to Low-Z[10]
CE HIGH to High-Z[10, 12]
25 35 ns
5 5 ns
20 25 ns
10 10 ns
20 25 ns
CE LOW to Power-up
0
0 ns
CE HIGH to Power-down
55 70 ns
BHE/BLE LOW to Data Valid
55 70 ns
BHE/BLE LOW to Low-Z[10]
5
5 ns
BHE/BLE HIGH to High-Z[10, 12] 20 25 ns
tWC
Write Cycle Time
55 70 ns
tSCE
CE LOW to Write End
45
60
ns
Notes:
7. Full-device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
8. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for
any given device.
11. If both byte enables are toggled together this value is 10 ns.
12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
13. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05201 Rev. *D
Page 5 of 13
5 Page 
Package Diagrams
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
48-ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A
51-85096-*E
Document #: 38-05201 Rev. *D
Page 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CY62137CV33.PDF ] | |
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