PDF CS4245 Data sheet ( Hoja de datos )

Número de pieza	CS4245
Descripción	105 dB / 24-Bit / 192 kHz Streo Sudio CODEC
Fabricantes	Cirrus Logic
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CS4245 104 dB, 24-Bit, 192 kHz Stereo Audio CODEC D/A Features  Multi-bit Delta Sigma Modulator  104 dB Dynamic Range  -90 dB THD+N  Up to 192 kHz Sampling Rates  Single-Ended Analog Architecture  Volume Control with Soft Ramp – 0.5 dB Step Size – Zero Crossing, Click-Free Transitions  Popguard® Technology – Minimizes the Effects of Output Transients  Filtered Line-Level Outputs  Selectable Serial Audio Interface Formats – Left-Justified up to 24-bit – I²S up to 24-bit – Right-Justified 16-, 18-, 20-, and 24-bit  Selectable 50/15 µs De-Emphasis  Control Output for External Muting A/D Features  Multi-bit Delta Sigma Modulator  104 dB Dynamic Range  -95 dB THD+N  Stereo 6:1 Input Multiplexer  Programmable Gain Amplifier (PGA) – ± 12 dB Gain, 0.5 dB Step Size – Zero Crossing, Click-Free Transitions  Stereo Microphone Inputs – +32 dB Gain Stage – Low-Noise Bias Supply  Up to 192 kHz Sampling Rates  Selectable Serial Audio Interface Formats – Left-Justified up to 24-bit – I²S up to 24-bit  High-Pass Filter or DC Offset Calibration 1.8 V to 5 V Serial Audio Input I2C/SPI Control Data Interrupt ADC Overflow Reset Serial Audio Output 3.3 V to 5 V 3.3 V to 5 V Volume Control Volume Control Interpolation Filter Interpolation Filter Multibit Modulator Multibit Modulator Switched Capacitor DAC and Filter Switched Capacitor DAC and Filter Register Configuration Internal Voltage Reference Mute Control MUX High Pass Filter Low-Latency Anti-Alias Filter High Pass Filter Low-Latency Anti-Alias Filter Multibit Oversampling ADC Multibit Oversampling ADC PGA MUX PGA +32 dB +32 dB Left DAC Output Mute Control Right DAC Output Left Aux Output Right Aux Output Stereo Input 1 Stereo Input 2 Stereo Input 3 Stereo Input 4 / Mic Input 1 & 2 Stereo Input 5 Stereo Input 6 http://www.cirrus.com Copyright  Cirrus Logic, Inc. 2012 (All Rights Reserved) AUG '12 DS656F3 1 page CS4245 LIST OF FIGURES Figure 1.DAC Output Test Load ................................................................................................................ 12 Figure 2.Maximum DAC Loading .............................................................................................................. 12 Figure 3.Master Mode Timing - Serial Audio Port 1 .................................................................................. 23 Figure 4.Slave Mode Timing - Serial Audio Port 1 .................................................................................... 23 Figure 5.Master Mode Timing - Serial Audio Port 2 .................................................................................. 25 Figure 6.Slave Mode Timing - Serial Audio Port 2 .................................................................................... 25 Figure 7.Format 0, Left-Justified up to 24-Bit Data ................................................................................... 26 Figure 8.Format 1, I²S up to 24-Bit Data ................................................................................................... 26 Figure 9.Format 2, Right-Justified 16-Bit Data. Format 3, Right-Justified 24-Bit Data. ....................................................................................................... 26 Figure 10.Control Port Timing - I²C Format ............................................................................................... 27 Figure 11.Control Port Timing - SPI Format .............................................................................................. 28 Figure 12.Typical Connection Diagram ..................................................................................................... 29 Figure 13.Master Mode Clocking .............................................................................................................. 32 Figure 14.Analog Input Architecture .......................................................................................................... 34 Figure 15.De-Emphasis Curve .................................................................................................................. 36 Figure 16.Suggested Active-Low Mute Circuit .......................................................................................... 37 Figure 17.Control Port Timing in SPI Mode .............................................................................................. 38 Figure 18.Control Port Timing, I²C Write ................................................................................................... 38 Figure 19.Control Port Timing, I²C Read ................................................................................................... 39 Figure 20.De-Emphasis Curve .................................................................................................................. 44 Figure 21.DAC Single-Speed Stopband Rejection ................................................................................... 53 Figure 22.DAC Single-Speed Transition Band .......................................................................................... 53 Figure 23.DAC Single-Speed Transition Band .......................................................................................... 53 Figure 24.DAC Single-Speed Passband Ripple ........................................................................................ 53 Figure 25.DAC Double-Speed Stopband Rejection .................................................................................. 53 Figure 26.DAC Double-Speed Transition Band ........................................................................................ 53 Figure 27.DAC Double-Speed Transition Band ........................................................................................ 54 Figure 28.DAC Double-Speed Passband Ripple ...................................................................................... 54 Figure 29.DAC Quad-Speed Stopband Rejection ..................................................................................... 54 Figure 30.DAC Quad-Speed Transition Band ........................................................................................... 54 Figure 31.DAC Quad-Speed Transition Band ........................................................................................... 54 Figure 32.DAC Quad-Speed Passband Ripple ......................................................................................... 54 Figure 33.ADC Single-Speed Stopband Rejection ................................................................................... 55 Figure 34.ADC Single-Speed Stopband Rejection ................................................................................... 55 Figure 35.ADC Single-Speed Transition Band (Detail) ............................................................................. 55 Figure 36.ADC Single-Speed Passband Ripple ........................................................................................ 55 Figure 37.ADC Double-Speed Stopband Rejection .................................................................................. 55 Figure 38.ADC Double-Speed Stopband Rejection .................................................................................. 55 Figure 39.ADC Double-Speed Transition Band (Detail) ............................................................................ 56 Figure 40.ADC Double-Speed Passband Ripple ...................................................................................... 56 Figure 41.ADC Quad-Speed Stopband Rejection ..................................................................................... 56 Figure 42.ADC Quad-Speed Stopband Rejection ..................................................................................... 56 Figure 43.ADC Quad-Speed Transition Band (Detail) .............................................................................. 56 Figure 44.ADC Quad-Speed Passband Ripple ......................................................................................... 56 LIST OF TABLES Table 1. Speed Modes .............................................................................................................................. 30 Table 2. Common Clock Frequencies ....................................................................................................... 31 Table 3. Slave Mode MCLK Dividers ........................................................................................................ 31 Table 4. Slave Mode Serial Bit Clock Ratios ............................................................................................. 32 Table 5. Device Revision .......................................................................................................................... 42 DS656F3 5 5 Page CS4245 6. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp’s stability. CL affects the dominant pole of the internal output amp; increasing CL beyond 100 pF can cause the internal op-amp to become unstable. DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Parameter (Note 7,10) Combined Digital and On-chip Analog Filter Response Symbol Min Typ Max Single-Speed Mode Unit Passband (Note 7) to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 8) Group Delay De-emphasis Error (Note 9) Fs = 44.1 kHz Combined Digital and On-chip Analog Filter Response tgd 0 - 0.35 0 - 0.4992 -0.175 - +0.01 0.5465 - - 50 - - - 10/Fs - - - +0.05/-0.25 Double-Speed Mode Fs Fs dB Fs dB s dB Passband (Note 7) to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 8) Group Delay Combined Digital and On-chip Analog Filter Response tgd 0- 0- -0.15 - 0.5770 - 55 - - 5/Fs Quad-Speed Mode 0.22 0.501 +0.15 - - - Fs Fs dB Fs dB s Passband (Note 7) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay to -0.1 dB corner to -3 dB corner (Note 8) tgd 0 0 -0.12 0.7 51 - - - - - - 2.5/Fs 0.110 0.469 0 - - - Fs Fs dB Fs dB s 7. Filter response is guaranteed by design. 8. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs. 9. De-emphasis is available only in Single-Speed Mode. 10. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this data (Figures 21 to 30) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. DS656F3 11 11 Page

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