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PDF MC33982 Data sheet ( Hoja de datos )
| Número de pieza | MC33982 | |
| Descripción | Single Intelligent High-Current Self-Protected Silicon High-Side Switch | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33982/D
Rev 7.0, 03/2004
Preliminary Information
Single Intelligent High-Current
Self-Protected Silicon High-Side
Switch (2.0 mΩ)
The 33982 is a self-protected silicon 2.0 mΩ high-side switch used to
replace electromechanical relays, fuses, and discrete devices in power
management applications. The 33982 is designed for harsh environments,
and it includes self-recovery features. The device is suitable for loads with high
inrush current, as well as motors and all types of resistive and inductive loads.
Programming, control, and diagnostics are implemented via the Serial
Peripheral Interface (SPI). A dedicated parallel input is available for alternate
and pulse width modulation (PWM) control of the output. SPI programmable
fault trip thresholds allow the device to be adjusted for optimal performance in
the application.
The 33982 is packaged in a power-enhanced 12 x 12 PQFN package with
exposed tabs.
Features
• Single 2.0 mΩ Max High-Side Switch with Parallel Input or SPI Control
• 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 µA
• Output Current Monitoring Output with Two SPI-Selectable Current
Ratios
• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time,
Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout, Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads,
Overtemperature Shutdown, Undervoltage and Overvoltage Shutdown,
Fail-Safe Terminal Status, and Program Status
• Enhanced 16 V Reverse Polarity VPWR Protection
33982
SINGLE HIGH-SIDE SWITCH
2.0 mΩ
PNA SUFFIX
CASE 1402-02
1S6-TCEARMLINEAL1P:Q1FN
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC33982PNA/R2 -40°C to 125°C 16 PQFN
3398S2imSpilmifiepdliAfpiepdlicAatipopn lDiciaagtriaomn Diagram
VDD VDD
I/O
I/O
SO
SCLK
MCU CS
SI
I/O
I/O
A/D
VDD VPWR
33982
VDD VPWR
FS GND
WAKE
SI
SCLK
CS
SO HS
RST
IN LOAD
CSNS
FSI GND
GND PWRGND
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 2004
For More Information On This Product,
Go to: www.freescale.com
1 page  
Freescale Semiconductor, Inc.
MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Operating Voltage Range
Steady-State
Symbol
VPWR
Value
-16 to 41
Unit
V
VDD Supply Voltage
VDD
0 to 5.5
V
Input/Output Voltage (Note 1)
SO Output Voltage (Note 1)
WAKE Input Clamp Current
CSNS Input Clamp Current
Output Current (Note 2)
Output Clamp Energy (Note 3)
Storage Temperature
Operating Junction Temperature
Thermal Resistance (Note 4)
Junction to Case
Junction to Ambient
ESD Voltage
Human Body Model (Note 5)
Machine Model (Note 6)
VIN, RST, FSI,
CSNS, SI, SCLK,
CS, FS
VSO
ICL(WAKE)
ICL(CSNS)
IOUT
ECL
TSTG
TJ
RθJC
RθJA
VESD1
VESD2
-0.3 to 7.0
-0.3 to VDD+0.3
2.5
10
60
1.5
-55 to 150
-40 to 150
<1.0
20
± 2000
± 200
V
V
mA
mA
A
J
°C
°C
°C/W
V
Terminal Soldering Temperature (Note 7)
TSOLDER 240 °C
Notes
1. Exceeding voltage limits on IN, RST, FSI, CSNS, SI, SO, SCLK, CS, or FS terminals may cause a malfunction or permanent damage to the
device.
2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
3. Active clamp energy using single-pulse method (L = 16 mH, RL = 0, VPWR = 12 V, TJ = 150°C).
4. Device mounted on a 2s2p test board according to JEDEC JESD51-2.
5. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
6. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω) and in accordance with the system module
specification with a capacitor > 0.01 µF connected from HS to GND.
7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
MOTOROLA ANALOG INTEGRATED CIRFCoUrITMDEoVrIeCEIDnAfoTArmation On This Product,
Go to: www.freescale.com
33982
5
5 Page 
Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ Max Unit
POWER OUTPUT TIMING (continued)
Output Turn-ON Delay Time in Fast/Slow Slew Rate (Note 20)
DICR = 0, DICR = 1
tDLY(ON)
1.0
µs
18 100
Output Turn-OFF Delay Time in Slow Slew Rate Mode (Note 21)
DICR = 0
tDLY_SLOW(OFF)
20
µs
230 500
Output Turn-OFF Delay Time in Fast Slew Rate Mode (Note 21)
DICR = 1
tDLY_FAST(OFF)
10
µs
60 200
Direct Input Switching Frequency (DICR D3 = 0)
Overcurrent Detection Blanking Time (OCLT[1:0])
00
01
10
11
Overcurrent High Detection Blanking Time
CS to CSNS Valid Time (Note 22)
fPWM
tOCL0
tOCL1
tOCL2
tOCL3
tOCH
CNSVAL
–
108
7.0
0.8
0.08
1.0
–
300
155
10
1.2
0.15
10
–
–
202
13
1.6
0.25
20
10
Hz
ms
µs
µs
Output Switching Delay Time (OSD[2:0])
000
001
010
011
100
101
110
111
ms
tOSD0
–
0
–
tOSD1
52
75
95
tOSD2
105
150
195
tOSD3
157
225
293
tOSD4
210
300
390
tOSD5
262
375
488
tOSD6
315
450
585
tOSD7
367
525
683
Watchdog Timeout (WD[1:0]) (Note 23)
00
01
10
11
tWDTO0
tWDTO1
tWDTO2
tWDTO3
434
207
1750
875
620
310
2500
1250
806
403
3250
1625
ms
Notes
20. Turn-ON delay time measured from rising edge of any signal (IN, SCLK, CS) that would turn the output ON to VOUT = 0.5 V with RL = 5.0 Ω
resistive load.
21. Turn-OFF delay time measured from falling edge of any signal (IN, SCLK, CS) that would turn the output OFF to VOUT = VPWR-0.5 V with
RL = 5.0 Ω resistive load.
22. Time necessary for the CSNS to be within ±5% of the targeted value.
23. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output driven
OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts.
MOTOROLA ANALOG INTEGRATED CIRFCoUrITMDEoVrIeCEIDnAfoTArmation On This Product,
Go to: www.freescale.com
33982
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MC33982.PDF ] | |
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