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PDF MSC1212-01 Data sheet ( Hoja de datos )
| Número de pieza | MSC1212-01 | |
| Descripción | 48-Bit Grid/Anode Driver | |
| Fabricantes | OKI electronic componets | |
| Logotipo |  |
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E2C0021-27-Y3
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MSC1212-01
48-Bit Grid/Anode Driver
This versionM: NSCov1.211929-701
Previous version: Jul. 1996
GENERAL DESCRIPTION
The MSC1212-01 is a driver IC for VFD implemented in BiCMOS technology.
The circuit consists of a 48-bit shift register and a 48-bit latch; they control display data, which
is output from the display drivers.
Since a 64-pin plastic QFP package is used, the display unit size can be reduced.
FEATURES
• Logic supply voltage (VCC)
• Driver supply voltage (VDISP)
• Operating temperature range
: 4.5 to 5.5 V
: 8 to 18 V
: –40 to +105°C
• Driver output current
: IO2-1 = –6 mA (for only one driver on state)
IO2-2 = –50 mA (total current for all drivers on
state)
• Built-in 48-bit output Driver (with latch)
IO2-3 = 0.2 mA
• Built-in 48-bit shift register
• Clock frequency
: 0.5 MHz
• Package:
64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: MSC1212-01GS-BK)
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¡ Semiconductor
PIN DESCRIPTION
Function
Driver Output
Driver Power Supply
Logic Power Supply
Driver GND
Logic GND
Data Input
Pin
1 to 17
32 to 48
50 to 63
19, 30
27
20, 29
21
22
Clock Input
23
Latch Strobe Input
24
Clear Input
25
Test Input
Data Output
26
28
MSC1212-01
Symbol
HVO1
to
HVO48
VDISP
VCC
D-GND
L-GND
DIN
CLK
LS
CL
CHG
DOUT
Description
Driver output pins, applicable to each bit of shift
register.
Power supply pins for driver circuit. Both Pin 19
and 30 should be connected externally.
Power supply pin for logic.
GND pins for the driver circuit.
Both Pin 20 and 29 should be connected externally.
GND pin for the logic circuit.
Input pin without pull-up or pull-down resistor.
Input pin of shift register. Display data input is
synchronized with clock signal. (positive logic)
Input pin without pull-up or pull-down resistor.
Data of shift register is shifted from one stage to
the next on application of each clock rising edge.
Input pin without pull-up or pull-down resistor.
When LS is at "H" level, the latch is shunted and the
shift register output becomes the lacth output.
When LS is at "L" level, the lacth holds the shift
register output just bafore LS goes to "L" level.
Clear input pin with pull-up resistor. Normally "L"
level. In this condition, driver output changes to "H"
or "L" according to latch output level. When CL is
"H", all driver output pins are fixed to "L".
Test input pin with pull-down resistor. Normally "L"
level, but here, if CL="H", then driver output changes
to "H" or "L" according to latch output level.
If CL = "L" when CHG is at "H" level, all driver output
is fixed to "H" for test.
Serial output pin of shift register.
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¡ Semiconductor
PACKAGE DIMENSIONS
QFP64-P-1414-0.80-BK
MSC1212-01
(Unit : mm)
Mirror finish
Notes for Mounting the Surface Mount Type Package
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.87 TYP.
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet MSC1212-01.PDF ] | |
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